Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2001-05-01
2004-06-08
Dildine, R. Stephen (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S752000
Reexamination Certificate
active
06748567
ABSTRACT:
FIELD OF INVENTION
The present invention relates to error checking and correction (ECC) codes, and particularly to the use of ECC codes in DC-balanced, asynchronous communication, such as communication over optical fiber.
BACKGROUND
To save on the number of wires or optical fibers, telecommunications signals are typically transmitted serially and asynchronously. Frequently these signals will be sent between devices such as integrated circuits or circuit boards, so that generally fewer I/O pins and connectors (such as backplane connectors or cable connectors) will be used. Unfortunately, I/O pins and connectors are typically some of the most likely parts of a system to cause single-bit errors in the signals being communicated.
Error checking and correction codes (ECC codes) are often used in a system on data that has a higher than desired chance of becoming corrupted. The ability for an ECC code to detect and correct bit failures depends upon the ECC code utilized. Some ECC codes are designed to detect and correct a burst of errors (several closely spaced errors). Other ECC codes may only repair a single-bit error and detect (but not repair) when two or more bits have failed. Some ECC codes may not be able to detect multiple bit failures. But with any ECC code, when a failure is detected, the ECC code is usually used to generate a “syndrome.” The value of the syndrome is generally used to detect and correct bits that have changed state since the ECC code was originally generated at the transmitting entity.
Moreover, once data is transmitted over an asynchronous, serial link, in order for the receiving entity to recover the data communicated with reasonable accuracy, the receiving entity generally needs to identify the rate at which the data was transmitted by the transmitting entity. In other words, the receiving entity needs to recover the clock used by the transmitting entity. In order to recover the clock the receiving entity generally needs to see a certain rate of change between ones and zeros because the transition from one to zero or zero to one is a reliable indicator of a clock edge. If there are too few transitions from one to zero or zero to one, a clock may not be accurately recovered. Further, a significant imbalance between the number of 0's and the number of 1's in the encoded data stream can cause severe loss of waveform integrity on AC coupled links, since any DC content cannot be transmitted and this information is simply lost at the receiver. To some extent, this loss can be accommodated by providing a higher bandwidth transmission medium or by using special compensation techniques at the receiver. However, it is much better to employ codes that are free of any net DC component, so as to gain the advantages of lower error rates. Accordingly, the transmitted signal should be “DC balanced,” having approximately the same number of ones and zeros.
When optically communicating over fiber, 8-bit characters (sometimes each character is referred to as a “byte”) are frequently converted to 10-bit characters before the data is sent over the optical connection. This conversion is sometimes referred to herein as “8b10b conversion.” Still, these 10-bit characters should be DC balanced as well. There are well-known methods and tables for performing 8b10b conversion in a manner that strives for DC balance, such as that described in Franaszek et al., U.S. Pat. No. 4,486,739, issued Dec. 4, 1984, and by Stevens, U.S. Pat. No. 5,025,256, issued Jun. 18, 1991. Although many of the 10-bit characters may not each be perfectly DC balanced, over time such balance can be accomplished by monitoring the running disparity between ones and zeros. If there are more ones, the disparity is positive. If there are more zeros, the disparity is negative. And if there are approximately an equal number of ones and zeros, the disparity is neutral. For example, 1110110011 results in a positive running disparity (more ones than zeros), so the next 10-bit character will generally be selected to have a negative or neutral disparity. Not only is neutral disparity accomplished over time, but every character has enough transitions to recover a clock. Basically, these qualities can be achieved in part by each 8-bit character having either two 10-bit representations (one with a positive disparity and one with a negative disparity) or one 10-bit representation with neutral disparity. The 10-bit representation selected at a particular moment is a function of the current state of the overall monitored running disparity of the transmitted stream. Thus the 10-bit characters are selected in such a manner as to maintain the transmitted disparity within certain limits.
Data is generally transmitted in “packets” or “cells.” A given ECC code is typically computed to cover the particular cell it is associated with and is usually transmitted with the cell it covers. However, using the ECC code in the 10-bit domain is not easily done.
If the ECC code is designed to detect and repair a single-bit error in a cell, but the ECC code is generated in the 8-bit domain (undergoing 8b10b conversion with the rest of the cell), then when a 1-bit error occurs in transit, the failing bit will result in an erroneous 10-bit character. This erroneous 10-bit character will then be converted to an erroneous 8-bit character, which may differ from the original 8-bit character by more then one bit. The ECC code may not fix the failure in this case, and may not even detect the error.
The ECC code may also be generated in the 10-bit domain—after 8b10b conversion of the cell. But when the ECC code is generated from 10-bit characters, many different ECC codes may be produced, but most of them will violate the 10-bit data stream encoding rules, e.g., DC balance is not maintained or the ECC code mimics special control characters defined for the 10-bit domain.
Accordingly, a system or method that can produce a reliable error correction mechanism while maintaining DC balance and permitting clock recovery in the signal transmitted is desirable.
SUMMARY
An embodiment of a method and system is disclosed that provides a reliable ECC code that is transmitted as part of a serial stream. In some embodiments the ECC code is designed to be part of a serial stream that maintains DC balance and allow clock recovery. To provide such an ECC code, in one embodiment, a base ECC code is first generated from the 10-bit cell body. The base ECC code is divided into smaller portions that are each converted to the 10-bit domain in such a manner as to provide DC balance and allows clock recovery when transmitted with the cell body. Hence, the ECC code is represented by an expanded number of bits in one embodiment. Further, the integrity of the ECC code can be checked to determine if there is an error in the transmitted ECC code itself. In one embodiment the integrity of the ECC code is checked by checking the parity of the transmitted ECC code.
More specifically, in an embodiment where an ECC code is generated, the ECC code is divided into smaller portions. Those smaller portions are converted to 8-bit characters. The 8-bit characters are converted to 10-bit characters of a selected parity in a manner that provides DC balance to the overall transmitted data stream. When received, the parity of the 10-bit characters is checked. If the parity does not match the selected parity, an error in the ECC code is indicated. If the parity does match, then the ECC code is used to verify the integrity of and repair errors in the rest of the data cell covered by the ECC code. Subsequently, the data can be converted back to the 8-bit domain.
In this manner, ECC codes can be utilized in the serial 10-bit domain with data cells that undergo 8b10b conversion while maintaining DC balance and having sufficient 0-1 and 1-0 transitions to allow clock recovery.
REFERENCES:
patent: 4486739 (1984-12-01), Franaszek et al.
patent: 5025256 (1991-06-01), Stevens
patent: 5450421 (1995-09-01), Joo et al.
patent: 6198413 (2001-03-01), Widmer
Catherine A. French et al., Alternative Modul
Chui Gene K.
Norrie Christopher I. W.
Ornes Matthew D.
Dildine R. Stephen
Gimlan Gideon
MacPherson Kwok & Chen & Heid LLP
ZettaCom, Inc.
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