Method and system for equivalence checking of a low power...

Details Method and system for equivalence checking of a low power... Method and system for equivalence checking of a low power...

2006-10-25

2010-02-23

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07669165

ABSTRACT:
Method and system for equivalence checking of a low power design are disclosed. The method includes receiving a register-transfer level (RTL) netlist representation of a circuit, receiving a power specification file for describing power requirements of the circuit, creating a low power gate netlist for representing a design implementation of the circuit using the RTL netlist and the power specification file, creating a reference low power RTL netlist for representing a design specification of the circuit using the RTL netlist and the power specification file, and performing equivalence checking between the low power gate netlist and the reference low power RTL netlist. The method further includes annotating low power information described in the power specification file into the reference low power RTL netlist, and creating low power logic in the reference low power RTL netlist.

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Kanno et al., Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor, 2006 IEEE International Conference on Solid-State Circuits Digest of Technical Papers, Feb. 2006, pp. 2200-2209.
Viswanath et al., “Automatic Insertion of Low Power Annotations in RTL for Pipelined Microprocessors”, Proceedings of Design, Automation, and Test in Europe 2006, vol. 1, pp. 1-6, Mar. 2006.

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