Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-06-02
2008-03-11
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07343573
ABSTRACT:
A method, system and computer program product for performing verification of an electronic design is disclosed. The method includes receiving a design, including a first target set, a primary input set, and a first register set comprising one or more registers. A binary decision diagram analysis of the design is generated. A recursive extraction of one or more next states of selected registers is generated using the binary decision diagram analysis of the first target set and the primary input set. The recursive extraction is decomposed to generate a second target set, and the second target set is verified.
REFERENCES:
patent: 6131078 (2000-10-01), Plaisted
Bertacco et al., The Disjunctive Decomposition of Logic Functions, International Conference on Computer-Aided Design, 1997, pp. 78-82.
Sistla et al., Symmetry and Reduced Symmetry in Model Checking, International Conference on Computer Aided Verification, 2001, pp. 91-103.
Baumgartner Jason Raymond
Kanzelman Robert Lowell
Mony Hari
Paruthi Viresh
Dillion & Yudell LLP
Do Thuan
International Business Machines - Corporation
Salys Casimer K.
LandOfFree
Method and system for enhanced verification through binary... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for enhanced verification through binary..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for enhanced verification through binary... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3961784