Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1993-01-08
1999-04-27
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
39580003, 395382, 395391, 395393, 395872, 711 5, 711168, 711169, G06F 1516
Patent
active
058988823
ABSTRACT:
A method and system for permitting single cycle instruction dispatch in a superscalar processor system which dispatches multiple instructions simultaneously to a group of execution units for execution and placement of results thereof within specified general purpose registers. Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers are provided and each time an instruction is dispatched to an available execution unit, a particular one of the intermediate storage buffers is assigned to any destination operand within the dispatched instruction, permitting the instruction to be dispatched within a single cycle by eliminating any requirement for determining and selecting the specified general purpose register or a designated alternate general purpose register.
REFERENCES:
patent: 4051551 (1977-09-01), Lawrie et al.
patent: 5136697 (1992-08-01), Johnson
Sohi, "Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers," 1990, 349-359.
Kahle James Allan
Kau Chin-Cheng
Ogden Aubrey Deene
Poursepanj Ali Asghar
Tu Paul Kang-Guo
Dillon Andrew J.
International Business Machines - Corporation
Salys Casimer K.
Swann Tod R.
Tran Denise
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