Method and system for enforcing consistent per-physical page...

Details Method and system for enforcing consistent per-physical page... Method and system for enforcing consistent per-physical page...

2006-06-13

2006-06-13

Thai, Tuan V. (Department: 2186)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S141000, C711S154000

Reexamination Certificate

active

07062631

ABSTRACT:
A method and system for enforcing consistent per-physical page cacheability attributes is disclosed. The method for enforcing consistent per-physical page cacheability attributes maintains memory coherency within a processor addressing memory, such as by comparing a desired cacheability attribute of a physical page address in a PTE against an authoritative table that indicates the current cacheability status. This comparison can be made at the time the PTE is inserted into a TLB. When the comparison detects a mismatch between the desired cacheability attribute of the page and the page's current cacheability status, corrective action can be taken to transition the page into the desired cacheability state.

REFERENCES:
patent: 6189074 (2001-02-01), Pedneau
patent: 6304944 (2001-10-01), Pedneau
patent: 6738864 (2004-05-01), Chauvel
patent: 6779085 (2004-08-01), Chauvel
patent: 6839813 (2005-01-01), Chauvel

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