Method and system for eliminating adjacent address collisions on

Details Method and system for eliminating adjacent address collisions on Method and system for eliminating adjacent address collisions on

1998-06-19

2000-09-19

Etienne, Ario

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710 36, 710109, 710126, 710220, 710240, G06F 1300, G06F 13376

Patent

active

061226920

ABSTRACT:
Described is an apparatus for eliminating early retrying of PAAM address conflicts on a system bus with multiple processors connected by a non-master processor, by comparing addresses of the current master processor to the next transaction to be issued by the non-master processor. If the addresses are the same and a PAAM window is detected, the non-master processor will switch the next transaction type to be issued, to a null type transaction. Even though the addresses match, the PAAM window is ignored for a null type transaction. The null transaction type insertion by the non-master processor reduces the latency of a PAAM self retried operation and avoids a possible livelock condition by breaking the processors out of the livelock. This allows the processors to stop retrying and leave the bus. The processors are able to immediately arbitrate instead of delaying past the astat window and increasing bus latency.

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