Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1998-08-18
2001-05-01
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S150000, C711S167000, C711S168000
Reexamination Certificate
active
06226708
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to microprocessors and more particularly to a method and system for efficiently programming non-volatile memory in a microprocessor.
BACKGROUND OF THE INVENTION
Non-volatile memory retains information in the absence of power. Examples of non-volatile memory include erasable programmable read-only memory (EPROM) and electrically erasable programmable read-only memory (EEPROM). Non-volatile memory may be used in a variety of electronic devices to provide storage capability, including for example, microprocessors and, more particularly, microcontrollers.
Programming or writing to non-volatile memory is conventionally much slower than reading from non-volatile memory. This contrasts with volatile memory, in which the time required to read and write data are similar. This phenomena may be understood with reference to FIG.
1
.
FIG. 1
illustrates one example of a portion of a non-volatile memory, showing a floating-gate field-effect transistor
10
that functions as a memory cell that is part of an EEPROM memory array. In this example, floating-gate field-effect transistor
10
is an n-channel metal oxide semiconductor. Floating-gate field-effect transistor
10
includes a control gate
12
, which controls the programming operations of floating-gate field-effect transistor
10
, a floating gate
14
, which stores an electrical charge, a drain
16
, a source
18
, and a channel region
15
disposed between source
18
and drain
16
.
To program floating-gate field-effect transistor
10
, a relatively high voltage is applied to control gate
12
and drain
16
simultaneously. As a result of this excitation, some of the electrons in channel region
15
acquire enough energy to be transported from channel region
15
via a thin oxide layer
20
to floating gate
14
, as indicated by arrow
19
. This captured negative charge leaves channel
15
more positive and, hence, less conducting. As a result, the threshold voltage at control gate
12
is higher for a charged cell than for one that has no charge on floating gate
14
. Consequently, for a given voltage applied to control gate
12
, floating-gate field-effect transistor
10
will conduct if floating gate
14
is not charged and remain non-conducting if the floating gate
14
is charged with stored electrons. Therefore, a one or a zero may be stored by floating-gate field effect transistor
10
based on whether or not current flows through the transistor. Discharge of electrons from floating gate
14
is illustrated by arrows
22
.
Charging or discharging, and therefore programming or writing to floating gate
14
, may be time consuming for several reasons. First, the time required for electrons to move from channel
15
through oxide layer
20
, and onto floating gate
14
is significant. In addition, charging floating gate
14
may cause damage to oxide layer
20
between channel
15
and floating gate
14
because of a resulting electric field. Therefore, charging should be performed slowly to protect the integrity of oxide layer
20
.
A plurality of non-volatile memory cells may be grouped to form an addressable location within a non-volatile memory array. Addressable locations typically include eight or sixteen bits. A non-volatile memory array may be contained on a non-volatile memory module along with control registers and additional circuitry that controls access to the non-volatile memory array. A plurality of non-volatile memory modules may be contained within one electronic device. In some prior electronic devices, only one address location in each non-volatile memory module may be accessed at a given time. Therefore, because the time required to program the addressable location is substantial, programming all non-volatile memory arrays within an electronic device may be very time consuming. In addition, the use of a plurality of non-volatile memory modules conventionally leads to a large number of peripheral select lines required to access each non-volatile memory module. Requiring a large number of peripheral select lines is undesirable, for example, because it may exhaust the limited number of peripheral select lines that are available and it reduces the efficiency of the code.
SUMMARY OF THE INVENTION
Therefore a need has arisen for a method and system for efficiently programming non-volatile memory that address the disadvantages and deficiencies of prior systems and methods. The invention includes a method and system for efficiently programming non-volatile memory.
A method of writing a plurality of data values to a plurality of non-volatile memory modules connected to a processor includes initiating writing of a first data value to a first non-volatile memory array and delaying processing by the processor for a predetermined time to allow the first data value to be written to the first non-volatile memory array. The method further includes initiating writing of a second data value to a second non-volatile memory array before delaying processing by the processor to allow the processor to delay processing while both the first data value and the second data value are being written.
According to another aspect of the invention, a microprocessor includes a central processing unit and a memory system accessible by the central processing unit. The memory system includes memory divided into a plurality of non-volatile memory modules with each non-volatile memory module including a non-volatile memory array and a control register associated with the non-volatile memory array. The microprocessor also includes a common control register select line connecting the central processing unit to each control register in the plurality of non-volatile memory modules for providing access to the plurality of non-volatile memory arrays by the central processing unit.
The invention provides several technical advantages. For example, according to the invention the amount of time required to write to all cells of a non-volatile memory system is reduced by, at least in part, splitting a non-volatile memory system into a plurality of memory arrays, each memory array stored on a separate module having a separate control register. Because each memory has a separate control register, multiple memory cells may be written to, or programmed, at the same timel In addition, according to the invention, the number of peripheral select lines required for memory modules is reduced by connecting the memory modules to a common control register select bus.
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patent: 5649161 (1997-07-01), Andrade et al.
patent: 5740112 (1998-04-01), Tanaka et al.
patent: 5831929 (1998-11-01), Manning
patent: 5949716 (1999-09-01), Wong et al.
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Computer System Architecture, Third Edition, pp 42-43, M. Morris Mano, 1993.
Allan Andrew J.
McGoldrick Robert F.
Brady, III W James
Chace Christian P.
Kim Matthew
Marshall, Jr. Robert D.
Telecky , Jr. Frederick J.
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