Method and system for efficient validation of clock skews...

Details Method and system for efficient validation of clock skews... Method and system for efficient validation of clock skews...

2011-07-26

2011-07-26

Levin, Naum (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Logic design processing

C716S105000, C716S106000, C716S134000, C703S019000

Reexamination Certificate

active

07987440

ABSTRACT:
A method and a system for validating clock skews during a hierarchical static timing analysis of a chip or multi-chip package. Each pair of clock inputs of a hierarchical module bounds the allowable clock skew, creating new relative constraints on clock input arrival times propagated to those clock inputs. One embodiment is based on asserted arrival times and a maximum of computed slack values at said clock inputs, while a second embodiment is based on asserted arrival times and a minimum of downstream test slack values. The method further converts module clock assertions into a set of relative timing constraints to allow a hierarchical timing sign-off even in circumstances where absolute timing arrivals are not totally known at the time of module analysis.

REFERENCES:
patent: 7103863 (2006-09-01), Riepe et al.
patent: 7243320 (2007-07-01), Chiu et al.
patent: 7243323 (2007-07-01), Williams et al.
patent: 7428716 (2008-09-01), Visweswariah
patent: 7624364 (2009-11-01), Albrecht et al.
patent: 2005/0177357 (2005-08-01), Amatangelo et al.
patent: 2006/0247906 (2006-11-01), Austin et al.
patent: 2008/0209373 (2008-08-01), Buck et al.

Affiliated with

Also associated with

Rating

Method and system for efficient validation of clock skews... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and system for efficient validation of clock skews..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for efficient validation of clock skews... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2710837