Electrical computers and digital processing systems: memory – Address formation – Operand address generation
Patent
1995-08-25
1998-06-09
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Address formation
Operand address generation
711 4, 711220, 395376, 395377, 395391, 395394, G06F 926, G06F 1202
Patent
active
057652155
ABSTRACT:
A method and system are disclosed for managing the deallocation of a rename buffer allocated to an update instruction within a processor. The processor has a number of rename buffers for temporarily storing information associated with instructions executed by the processor, a number of registers, and a memory. According to the present invention, an update instruction is dispatched to the processor for execution. A particular rename buffer is then allocated to the update instruction. An effective address is generated for the update instruction, wherein the effective address specifies an address within the memory to be accessed by the update instruction. Next, the effective address is stored within the particular rename buffer. Prior to completion of the access to the effective address within memory, the effective address is transferred from the particular rename buffer to a particular one of the number of registers. Thereafter, the particular rename buffer is deallocated, wherein processor performance is enhanced by improved rename buffer availability.
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Afsar Muhammad
Mallick Soummya
Patel Rajesh B.
Chan Eddie P.
Dillon Andrew J.
International Business Machines - Corporation
Motorola Inc.
Nguyen Than V.
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