Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1994-10-05
1997-09-16
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711108, 711118, G06F 1212
Patent
active
056689721
ABSTRACT:
A data cache array which includes a plurality of cache lines wherein each cache line includes a selected block of data, a parity field, a content addressable field containing at least a portion of an address for that block of information and a data status field for providing an indication of data validity within that cache line. An allocation control cell is associated with each cache line and a pseudo least recently utilized (PLRU) logic circuit is provided within the data cache array for each group of cache lines. The pseudo least recently utilized (PLRU) logic circuit is then utilized to select and set a particular allocation control cell within each group of cache lines in response to utilization of those cache lines. The cache line allocation process is then utilized to select a particular cache line within a group of cache lines for replacement in response to either an indication of invalidity of the block of information within that cache line or in response to the state of the pseudo least recently utilized (PLRU) logic circuit for that group of cache lines, if the block of information within every cache line within the group is indicated as valid.
REFERENCES:
patent: 4404653 (1983-09-01), Ruhman et al.
patent: 4532606 (1985-07-01), Phelps
patent: 4538241 (1985-08-01), Levin et al.
patent: 4538243 (1985-08-01), Zehner
patent: 4758982 (1988-07-01), Price
patent: 4791606 (1988-12-01), Threewitt et al.
patent: 4799192 (1989-01-01), Wade et al.
patent: 4831585 (1989-05-01), Wade et al.
patent: 4858180 (1989-08-01), Murdoch
patent: 4894799 (1990-01-01), Hanawa et al.
patent: 4965767 (1990-10-01), Kinoshita et al.
patent: 4991081 (1991-02-01), Bosshart
patent: 4991136 (1991-02-01), Mihara
patent: 5051949 (1991-09-01), Young
patent: 5126968 (1992-06-01), Hamamoto et al.
patent: 5218687 (1993-06-01), Ducousso et al.
patent: 5226005 (1993-07-01), Lee et al.
patent: 5267190 (1993-11-01), Easley et al.
patent: 5299147 (1994-03-01), Holst
patent: 5359564 (1994-10-01), Liu et al.
Hiroshi Kadota, Jiro Miyake, Ichiro Okabayashi, Toshinori Maeda, Tadashi Okamoto, Masaitsu Nakajima and Keiichi Kagawa, "A 32-bit CMOS Microprocessor with On-Chip Cache and TLB" IEEE Journal of Solid-State Circuits, pp. 800-807, No. 5, New York, Oct., 1987.
8107 IEEE Journal of Solid-State Circuits, "A ternary Content addressable Search Engine" Jon P. Wade and Charles G. Sodini, Aug. 24, 1989 pp. 1003-1013.
Jim Handy, "The Cache Memory Book", 1993, pp. 86 & 259.
Branson Brian David
Liu Peichun Peter
Chan Eddie P.
Davis, Jr. Michael A.
Dillon Andrew J.
Ellis Kevin L.
International Business Machines - Corporation
LandOfFree
Method and system for efficient miss sequence cache line allocat does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for efficient miss sequence cache line allocat, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for efficient miss sequence cache line allocat will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-225429