Method and system for efficient message validation

Details Method and system for efficient message validation Method and system for efficient message validation

1997-10-20

1999-09-28

Sheikh, Ayaz R.

Electrical computers and digital data processing systems: input/

Intrasystem connection

710105, G06F 1300

Patent

active

059580291

ABSTRACT:
A communications processor (30) includes a DMA controller (34) and a module associated with a broadcast communications protocol such as a CAN module (50), both connected to a common internal bus (36). The CAN module (50) includes a single comparator (56) for comparison of multiple identifier mask values with the identifier of a message transmitted on the CAN bus (25). The communications processor (30) also includes a random access memory (RAM) (40) which stores the multiple identifier mask values which the DMA controller (34) automatically transfers to the CAN module (50) without intervention by the CPU (32). In addition, the CAN module (50) provides a valid message interrupt to the CPU (32) only after the message has been validated and does not interrupt the CPU (32) when messages intended only for other nodes are encountered.

REFERENCES:
patent: 5027349 (1991-06-01), Thorne
patent: 5444626 (1995-08-01), Schenk
patent: 5469150 (1995-11-01), Sitte
patent: 5551053 (1996-08-01), Nadolski et al.
patent: 5675830 (1997-10-01), Satula
patent: 5801948 (1998-09-01), Wood et al.
Motorola, Inc. 1996, "HC08 HCMOS Microcontroller Unit Technical Summary", Section 23 mcCAN08 Controller, pp. 23-1 thru 23-33.
Motorola, Inc. 1996, "HC08 MC68HC08XL36 HCMOS Microcontroller Unit Technical Data", Direct Memory Access Module (DMA), pp. 107-140.

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