Electrical computers and digital data processing systems: input/ – Intrasystem connection – Protocol
Reexamination Certificate
2006-02-01
2010-02-16
Cleary, Thomas J (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Protocol
C710S003000, C710S260000, C714S799000, C714S807000
Reexamination Certificate
active
07664898
ABSTRACT:
A framing mechanism may be provided that enables passing of messages over an addressed bus. This creates a form of information hiding, which passes information by converting an addressed bus interface to a message-based bus interface. Address-based information in a transaction may be replaced with additional information that specifies framing details comprising, for example, a check pattern and length information. The check pattern provides a mechanism for determining whether frame information may be valid. An end device may utilize this length information to determine an actual length of an incoming frame. The combination of the check pattern and the length information may provide a pattern for resynchronizing a data stream when errors are detected. The framing mechanism may operate over existing addressed buses without requiring host side controller hardware modifications and additional host side software driver may be utilized to add the framing information.
REFERENCES:
patent: 4644529 (1987-02-01), Amstutz et al.
patent: 5537558 (1996-07-01), Fletcher et al.
patent: 5809068 (1998-09-01), Johnson
patent: 6028892 (2000-02-01), Barabash et al.
patent: 6101378 (2000-08-01), Barabash et al.
patent: 6363428 (2002-03-01), Chou et al.
patent: 6725413 (2004-04-01), Ishida
patent: 6760333 (2004-07-01), Moody et al.
patent: 7251704 (2007-07-01), Solomon et al.
patent: 2001/0047475 (2001-11-01), Terasaki
patent: 2001/0053148 (2001-12-01), Bilic et al.
patent: 2004/0054955 (2004-03-01), Riley
patent: 2004/0123221 (2004-06-01), Huffman et al.
patent: 2005/0105549 (2005-05-01), Ishida et al.
patent: 2006/0072564 (2006-04-01), Cornett et al.
patent: 2006/0098648 (2006-05-01), Fukunaga et al.
patent: 2006/0104227 (2006-05-01), Chuang
patent: 2007/0162981 (2007-07-01), Morioka et al.
“LAN Data Link Layer Protocols”. Protocol Directory. Online Aug. 17, 2000. Retrieved from Internet May 21, 2008. <http://web.archive.org/web/20000817202644/http://www.protocols.com/pbook/lan.htm>.
“Secure Digital Input/Output (SDIO) Card Specification”. Version 1.00. Oct. 2001. SD Association.
“Webopedia”. Entry 'SD Card'. Online Jan. 5, 2005. Retrieved from Internet May 23, 2008. <http://www.webopedia.com/TERM/S/SD—Card.html>.
“About PCMCIA”. Personal Computer Memory Card Internation Association. 1998. Retrieved from Internet Jan. 14, 2009. pp. 1-4. <http://web.archive.org/web/19990827013904/http://www.pcmcia.org/about.htm>.
Jin Changxi
Loyola Guillermo A.
Nuckolls Neal
Siener Stephen G.
Broadcom
Cleary Thomas J
McAndrews Held & Malloy Ltd.
LandOfFree
Method and system for efficient framing on addressed buses does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for efficient framing on addressed buses, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for efficient framing on addressed buses will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4154120