Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2000-03-20
2003-11-04
McLean-Mayo, Kimberly (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S144000
Reexamination Certificate
active
06643742
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to cache management design, and specifically to a system and method for analyzing and replacing cache memory locations.
2. Description of the Related Art
A computing system for processing information can include a system memory. Moreover, one or more processing modules of the system can include a cache memory. A cache memory is a relatively small high-speed memory that stores a copy of information from one or more portions of the system memory. For example, a cache memory could store 1 Million bits (1 M), and a system memory could store 1-100 Million bits. Normally, the cache memory is physically distinct from the system memory, and each processing module manages the state of its respective cache memory. Typically, a cache memory is located within a processor or on the same integrated circuit, and system memory is located at an external location on another logic board or module.
If a processor requests access to commonly used locations in the system memory, a memory controller copies a portion of the commonly used locations from the system memory into the processing module's cache memory. Copying the commonly used locations results in quicker access times due to the proximity and faster access times of the cache memory relative to the system memory and increases the processor's performance. In the event of a cache miss, a condition where the processor requests a certain address and data from a location in cache memory, but the cache memory does not contain the address, the cache memory requests the address from the system memory. However, the cache miss results in a significant system performance impact due to the relatively long time delay in waiting for the slower system memory to respond to the request and fetch the address and data. Eventually, the new address and data are stored at a location in the cache memory.
Efficient cache operation requires cache management techniques for replacing cache locations in the event of a cache miss. In the previous example of a cache miss, the address and data fetched from the system memory is stored in cache memory. However, the cache needs to determine which cache location is to be replaced by the new address and data from system memory. One technique for replacing cache locations is implementing least recently used bits and valid bits for each cache location. Least recently used bits are stored for each cache location and are updated when the cache location is accessed. Valid bits determine the coherency status of the respective cache location. Therefore, based on the value of the least recently used bits and the valid bits, the cache effectively replaces the cache locations where the least recently used bits indicate minimal activity or the location lacks coherency.
Present cache memory management logic are inefficient, requiring two read cycles, one read cycle for valid bits, and another separate read cycle for least recently used bits. Also, cache memory management logic requires dedicated and inflexible priority procedures for replacing least recently used cache locations.
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Beavens James A.
Vidwans Rohit
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
McLean-Mayo Kimberly
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