Electrical computers and digital processing systems: processing – Processing control – Processing control for data transfer
Reexamination Certificate
2011-07-05
2011-07-05
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Processing control for data transfer
C712S219000
Reexamination Certificate
active
07975130
ABSTRACT:
A method and system for early instruction text based operand store compare avoidance in a processor are provided. The system includes a processor pipeline for processing instruction text in an instruction stream, where the instruction text includes operand address information. The system also includes delay logic to monitor the instruction stream. The delay logic performs a method that includes detecting a load instruction following a store instruction in the instruction stream, comparing the operand address information of the store instruction with the load instruction. The method also includes delaying the load instruction in the processor pipeline in response to detecting a common field value between the operand address information of the store instruction and the load instruction.
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Alexander Khary J.
Busada Fadi Y.
Giamei Bruce C.
Hutton David S.
Shum Chung-Lung Kevin
Campbell John
Cantor & Colburn LLP
Coleman Eric
International Business Machines - Corporation
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