Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-03-30
2003-12-02
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06658631
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of computer systems. In particular, the present invention relates to generating resistance, capacitance and delay table look-ups for cell routers and placers.
BACKGROUND OF THE INVENTION
Computer Automated Design Tools (CAD), are developed for the placement and routing of cells during the design of integrated circuits. Cells are placed on the integrated circuit to meet specific design criteria such as minimizing the total length of the interconnects, power use, noise, or delay. One popular design criteria is the timing delay between two points connecting cells. There may be a maximum delay allowed, that is directly associated with a path that connects two points. The connection of two cells is called a net.
FIG. 1
illustrates a prior art integrated circuit including a net for interconnecting two or more nodes. Source node
120
, an AND gate, is connected via net
110
to OR gate
150
, NAND gate
140
, and NOR gate
130
. OR gate
150
, NAND gate
140
and NOR gate
130
are sink nodes
160
. Net
110
is in a fan-out configuration, although in alternate embodiments net
110
may only be connected to one other gate instead of three. In another embodiment, net
110
may not follow paths that are straight line paths to sink nodes
160
, but instead have jogs
111
, or bends in the wire connection. Net
110
may also include vias that bend wire connections through multiple metal layers in the integrated circuit
100
. Source node
120
, sink nodes
160
, and net
110
have associated capacitances, resistances and inductances. Net
110
has an associated delay for signals from source node
120
to sink nodes
160
. The delay is determined by multiple factors. These factors include the length, width, and height of net
110
, the resistance and capacitance of net
110
, source node
120
, and sink nodes
160
, the proximity of net
110
to other nets and nodes, the physical characteristics of the metal layers composing the integrated circuit and the number of vias and jogs in net
110
.
CAD systems perform resistance, capacitance, and delay (RCD) estimation, but only consider a limited number of these factors when generating RCD coefficients. For example, RCD estimation has been based on a wire model that only considers the length, width, and height of the net wire connections. Furthermore, the final routing of nets is rarely the same as the routing estimated by the wire model. The routing estimates used for wire models make it highly inaccurate. RCD estimation systems of the past also suffer from slow processing at placer run time. If the RCD data is not provided to the performance driven placer engine quickly, optimization can take days to complete due to the multiple iterations required by the placer.
SUMMARY OF THE INVENTION
The present invention provides a method and system for dynamically generating resistance, capacitance, and delay table look-ups. The system receives statistical data describing a new net as well as a desired level of accuracy. One or more preexisting net models are divided into one or more groups, wherein the number of groups is associated with the desired level of accuracy. The system returns a table of coefficients associated with the statistical data and the one or more groups.
REFERENCES:
patent: 5629860 (1997-05-01), Jones et al.
patent: 5636130 (1997-06-01), Salem et al.
patent: 6014508 (2000-01-01), Christian et al.
Levin Artour
Pyo Iksoo
Blakely , Sokoloff, Taylor & Zafman LLP
Bowers Brandon
Garbowski Leigh M.
Intel Corporation
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