Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2001-12-20
2003-10-28
Chang, Daniel (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C713S322000
Reexamination Certificate
active
06639428
ABSTRACT:
BACKGROUND
1 . Field of the Invention
The current invention is directed to a system and method for clocking a digital system. In particular, the current invention is directed to a dynamically adaptable clocking system and method based on power levels to the system.
2 . Description of the Art
Many constraints of typical digital systems may be traced to power usage. Generally speaking, power usage and peak power usage is of great importance in digital systems. These systems, including chips, devices on a chip, boards, such as graphics adapters, network interfaces, input/output devices, and complex digital systems, including personal digital assistants, palm devices, smart cards, notebook computers, and desktop computers, to name a few, use an electric current to power their systems. Typically, these digital devices use clocked semiconductor circuits in their processing flow.
As such, these synchronous digital systems expend the bulk of their power consumption when the clock signal changes state. This is even more critical in smaller systems, since the bulk of the power is provided through battery power. As such, the power budget for these smaller systems is smaller than one for a typical larger system. Even so, all of the systems have a maximum power budget to expend per clock cycle.
Many typical systems attempt to control the outflow of the power by limiting the number of clocks a circuit might see. Typically, this is accomplished by a clock division process. A hard ratio of clock division is designed in the circuitry. In particular, this is usually accomplished by dividing the clock into some fraction or ratio less than the original system clock. In this process, all the clocks may be seen, for full power, one of every two clocks may be seen, for half power, and so on. Typically, this is accomplished by simply estimating the number of cycles that the circuit should see, and manually implementing a hard-designed clock divisor into the circuitry.
In many typical processor-based systems, a further complication is added. This is because the current consumption is in control of the software running on the device.
In many typical applications running on such a processor, the programmer hard codes a specific clock division ratio consistent with the power budget of the system during specific instances of code execution. However, this is not optimal, since the ratio is constant across all circuitries. There is no easy ability to target individual circuitries in order to either mask clocks, or slow down clocks. Additionally, there is no easy way to target the subsystems based on the level of processing that they may be presently be employed to execute.
Assume that a typical system has three sets of logical circuitries, A, B, and C. In a first state, circuitry A runs at full speed while circuitries B and C are idle. If the clock division ratio is constant across the circuitries, the clocks available to the circuitries are wasted in this state, since the circuitries B and C need not run at full throttle in this state.
Additionally, assume that in state two, it does not matter that circuit B runs at full throttle, but it would be nice, but not essential, that it does so. If the power available to the entire system runs near a maximum power budget, it would not be beneficial for circuit B to run at full throttle when the other systems are enabled.
In other words, many typical systems have a set clocking speed. This speed ensures that the power draw at the peak computation does not exceed the operating budget. Thus, when the circuit is operating less intensely, it could go faster without breaching the power budget.
Changing the clock division ratio in software is not easily accomplished. In practice, this takes a good amount of extra code, effort, and verification that the budget is not exceeded. Additionally, when new chip sets are employed, their power signatures may not match those expected by the code designers. In this case, the dynamic software clocking does not meet the physical parameters of the new system, and the software is thus made obsolete.
In this manner, the typical clocking systems and methods suffer one or more shortcomings. Many other problems and disadvantages of the prior art will become apparent to one skilled in the art after comparing such prior art with the present invention as described herein.
SUMMARY
Aspects of the invention are found in a digital circuit having a regulated clock. The digital circuit is run in conjunction with a system clock signal. The digital circuit includes a digital logic circuitry that is regulated by a clock signal and powered by a system current.
The digital circuit also includes a clocking circuitry communicatively coupled to the digital logic circuitry. The system clock signal may also be supplied to the clocking circuitry. The clocking circuitry supplies a regulated clock signal to the digital logic circuitry.
The clocking circuitry includes a power supply monitor circuitry. The power monitor circuitry is coupled to the power supply and provides a signal indicative of the current or power consumed by the system.
The clocking circuitry also has a clock regulation circuitry. The clock regulation circuitry is coupled to the power supply monitoring circuitry and outputs a clock signal to the digital logic circuitry. The particular clock signal is based upon the signal indicative of system current.
More particularly, the particular clock signal is the system clock signal when the signal indicative of system current is in a first state. When the signal indicative of system current is in another state, a different modified clock signal is provided to the attached digital logic circuitry.
Additional aspects of the invention are found in such a digital circuit containing modal circuitry. The modal circuitry affects the clock output based upon the state reflected in the modal circuitry. As such, it may inhibit the changed clock, or override a default clock. The modal circuitry may be used in logical combinations with the signal indicative of system current to define differing clock states.
In one aspect, the trigger to effect the clock change is the comparison of the signal indicative of system current to a predetermined level of system current. In some cases, this predetermined level may be dynamically adaptable.
In other aspects of the invention, the power supply monitor circuitry may be made with a programmable current sink. In this manner, the current monitoring may be dynamically altered.
The power supply monitor circuitry may contain a voltage comparator. The voltage comparator can compare a voltage indicative of the system current and a first predetermined voltage. The power supply monitor circuitry can further contain a second voltage comparator. The second voltage comparator compares the voltage indicative of the system current to a second predetermined voltage.
In addition, the power supply monitor circuitry may have an analog to digital converter. The analog to digital converter produces signals on a plurality of output lines, where the signals on the plurality of output lines are indicative of the system current level.
The clock regulation circuitry may contain a clock inhibiting circuitry. The clock inhibiting circuitry prevents the assertion of a clock signal to the attached digital circuitry when the power usage for the system is too high.
The clock regulation circuitry may also be a clock reduction circuitry. In this case, the clock reduction circuitry outputs a second clock signal to the attached digital circuitry when power usage is too high. In this case, the second clock signal is slower than the system clock signal. This can be adaptively clocked accomplished with a clock divider.
Other aspects of the invention are found in a digital system with an adaptively regulated clocking cycle. The system is powered by a system current. The digital system has a system clock signal.
The digital system can contain a first logic circuitry clocked by a first clock signal and a second logic circuitry clocked by a second clock signal. The f
Barnett Philip C.
Green Andy
Advanced Technology & Materials Inc.
Chang Daniel
Chappuis Margaret
Hultquist Steven J.
Ryann William F.
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