Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-02-16
2010-02-16
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C438S617000
Reexamination Certificate
active
07665056
ABSTRACT:
Various embodiments of the present invention relate to a method, system, and computer program product for dynamic placement of various bond fingers on an integrated circuit (IC) package. This is achieved by determining the placement of selected bond fingers. Subsequently, bond fingers and bond wires are identified, which have been affected due to the placement of the selected bond fingers. Further, the placement of the selected and the affected bond fingers is determined based on clearance rules and the affected bond fingers and bond wires. This facilitates the dynamic placement of the various bond fingers in interaction with the user. Further, the user is provided with full interactive access and control over the method and system.
REFERENCES:
patent: 5245214 (1993-09-01), Simpson
patent: 6787901 (2004-09-01), Reyes et al.
patent: 2002/0042904 (2002-04-01), Ito et al.
patent: 2002/0084982 (2002-07-01), Rosenberg
patent: 2004/0017371 (2004-01-01), Shen et al.
Dean James A.
Keng Jean-Marc Ng Wing
Lockman Tyler James
Cadence Design Systems Inc.
Chiang Jack
Lin Aric
Rosenberg , Klein & Lee
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