Method and system for DRAM sensing

Details Method and system for DRAM sensing Method and system for DRAM sensing

2008-05-06

2008-05-06

Lam, David (Department: 2827)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S203000, C365S205000

Reexamination Certificate

active

07369425

ABSTRACT:
This invention discloses a dynamic random access memory (DRAM) device comprising a first bit-line coupled to a first terminal of at least one memory cell capacitor through one or more pass transistors, a second bit-line coupled to a first terminal of at least one reference cell capacitor through one or more pass transistors, and a cell plate connected to both a second terminal of at least one memory cell capacitor and a second terminal of at least one reference cell capacitor, wherein the cell plate is biased at approximately one half of a voltage difference between a positive supply voltage (Vdd) and a complementary lower supply voltage (Vss), and wherein the reference cell capacitor does not store any charge prior to a reading operation, and wherein both the first and second bit-lines are pre-charged to either Vdd or Vss prior to the reading operation.

REFERENCES:
patent: 5255232 (1993-10-01), Foss et al.
patent: 6226205 (2001-05-01), Guritz
Barth, John, et al., “A 300MHz Multi-Banked eDRAM Macro Featuring GND Sense, Bit-Line Twisting and Direct Reference Cell Write”, ISSCC 2002, Session 9, DRAM and Ferroelectric Memories, 9.3 (2002).

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