Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or...
Reexamination Certificate
1998-06-19
2002-01-01
Gossage, Glenn (Department: 2187)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
C711S118000, C711S173000, C712S023000, C712S217000
Reexamination Certificate
active
06336160
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to information handling systems and more particularly to an improved methodology for referencing information in registers of computer processing units.
BACKGROUND OF THE INVENTION
High performance superscalar computer processors use a technique known as “register renaming”to facilitate out-of-order instruction execution. In general, register renaming refers to a method by which a specific processor register may be used by multiple instructions without conflict. For example, if an instruction requires the use of a specific register, and a second instruction also requires the use of that same register while the register is still being used by the first instruction, the processor will redefine one of its unused registers as a second copy of the specific register, and the processor will track and manage the specific register and the renamed register relative to the information contained in the registers and the associated instructions.
Register renaming can also be used to redirect data held over in a rename register from the execution of a previous instruction for use by a subsequent instruction. However, such reuse of data values in rename registers is practically not achievable because rename registers get written over by new data values before the older values can be reused. Processors only have a very limited number of rename registers and adding too many such registers have other implementation performance-limiting aspects.
To date, processors have implemented register addressing on a whole unit basis. That is, register renaming is done by assigning an alias code to each operand on the basis of the register identifier and without regard to the portion of the bits of that register which are actually accessed by the instruction. This practice results in a waste of precious register bits.
As another consequence of implementing register addressing on a full register basis, if an instruction needs to access data bits in a register that are not aligned at the starting bit position of a register, such data has to be re-fetched from memory, hence, resulting in unnecessary performance degradation. For example, a typical RISC (Reduced Instruction Set Computer) processor, such as the PowerPC processor, was introduced as a 32-bit architecture and later extended to 64-bits. Existing applications written for the 32-bit processors must still run on the 64-bit processors. When the processor hardware assigns the architectural registers or the renamed registers to instructions, all the 64 register bits are used as a whole entity. However, half of the register bits are wasted when running 32-bit programs. In fact, the upper
32
bits of the register are left unused in many cases even in the 64-bit mode. The current processor design does not allow the upper and lower 32-bit halves of the 64-bit register to be equally accessible, which results in a waste of critical register bits.
Accordingly, there is a need for an enhanced method and processing apparatus which is able to provide increased register efficiencies and improved processor performance.
SUMMARY OF THE INVENTION
A method and apparatus is provided for sectoring processor registers and utilizing the most significant unused sectors of the processor registers to hold frequently used data. Since most register data values do not utilize the most significant bits of a register value, these most significant bits grouped as sectors can be utilized to provide enhanced performance resulting from data buffering. Unused register sectors are used to hold frequently used data or sequentially adjacent data to exploit spatial locality, thus, saving processor cycles to fetch data from the processor memory. In one embodiment, the register file is divided into sectors such that the smallest accessible unit for an instruction set in each register can be uniquely addressed and renamed. The most significant sectors of the registers, if not marked to be in use, are used for holding pre-assigned constant values, such as “0”, “1”, or other frequently used constant offsets, etc. In another embodiment, the previous data loaded into register sectors is saved in most significant register sectors for future possible reference by subsequent instructions.
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Eickemeyer Richard James
Malik Nadeem
Pita Alan Vicha
Saha Avijit
DeFrank Edmond A.
Emile Volel
Gossage Glenn
International Business Machines - Corporation
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