Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-12-07
2003-11-11
Elms, Richard (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185330, C365S185260, C365S185270
Reexamination Certificate
active
06646925
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to non-volatile memory devices and more particularly to a method and system for discharging the bit lines of a non-volatile memory after an erase operation.
BACKGROUND OF THE INVENTION
Non-volatile memory is used to store data in devices where data must be maintained when the device is not connected to a power supply. For example, non-volatile memory is used in personal computers to store the instructions for completing very basic tasks such as interfacing with a keyboard or accessing a disk drive. A common type of non-volatile memory is flash memory. Unlike many types of non-volatile memory, flash memory can be erased and rewritten.
To erase a flash memory cell, a large voltage is applied to the cell that erases the data stored in the cell. However, this process leaves an undesired charge on the bit line attached to the memory cell that must be eliminated. Previous attempts at solving this problem include attaching a discharge transistor to the bit line that is operable to create a connection to ground for discharging the bit line. A problem with this solution is that when a plurality of memory cells are configured as an array, the previous solution requires a separate transistor for each memory cell column. This results in memory cell arrays being unnecessarily large and, consequently, more expensive to produce.
SUMMARY OF THE INVENTION
Accordingly, a need has arisen for an improved method and system for discharging the charge remaining on the bit line of a memory cell after erasure. The present invention provides a system and method for discharging flash memory cell bit lines that addresses the shortcomings of prior systems and methods.
According to one embodiment of the invention, a method for use in erasing data stored in a memory cell includes asserting a voltage differential across a tank region and a gate region of the memory cell. The tank region has a first conductivity type and the tank region is located within a well region of a second conductivity type. The method also includes floating the voltage level of a source region and a drain region of the memory cell. The source region and the drain region are located within the tank region and have the second conductivity type. The method additionally includes discharging a charge stored in the drain region by electrically connecting the source region to an electric potential lower than the potential of the drain region and electrically connecting the well region and the tank region to a potential lower than their existing potentials.
According to another embodiment of the invention, a memory array includes a plurality of memory cells. Each memory cell includes a well region having a first conductivity type. The memory cell additionally includes a tank region located within the well region and having a second conductivity type. The memory cell also includes a source region located in the tank region. The source has the first conductivity type. The memory cell additionally includes a drain region located in the tank region. The drain region has the first conductivity type. The memory cell array also includes a switch connecting each source region to ground in a manner such that, when the switch is close, electrons will flow from the source region to the drain region.
Embodiments of the invention provide numerous technical advantages. For example, in one embodiment of the invention, a method is provided for discharging an entire memory cell array by means of one switch connected to a common source region of the memory array. Thus, a single transistor can be used to discharge each of the plurality of memory cells comprising the memory array. As a result, the silicon area of memory arrays can be reduced, leading to lower production costs.
Other technical advantages are readily apparent to one skilled in the art from the following figures, descriptions, and claims.
REFERENCES:
patent: 5907506 (1999-05-01), Jinbo
Heinrich-Barna Stephen K.
Kaya Cetin
Brady III W. James
Elms Richard
Hur Jung H.
McLarty Peter K.
Telecky , Jr. Frederick J.
LandOfFree
Method and system for discharging the bit lines of a memory... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for discharging the bit lines of a memory..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for discharging the bit lines of a memory... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3168005