Method and system for developing post-layout electronic data...

Details Method and system for developing post-layout electronic data... Method and system for developing post-layout electronic data...

2006-11-10

2010-10-19

Levin, Naum B (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C700S097000

Reexamination Certificate

active

07818708

ABSTRACT:
A method and system for processing geometrical layout design data to manufacture an electronic circuit is provided. The method includes extracting the geometrical layout design data from one or more data-format files. The method further includes segregating the geometrical layout design data extracted from one or more data-format files into each of a structural data, a spatial data, and a raw-geometry data. Thereafter, one or more predefined operations are performed on one or more of the structural data, the spatial data, and the raw-geometry data.

REFERENCES:
patent: 5530372 (1996-06-01), Lee et al.
patent: 7356374 (2008-04-01), Suttile et al.
patent: 7401319 (2008-07-01), Horng et al.
patent: 7546232 (2009-06-01), Brooks et al.

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