Method and system for determining which memory locations have be

Details Method and system for determining which memory locations have be Method and system for determining which memory locations have be

1997-04-28

2000-09-05

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

714726, 714719, 714733, 711108, G06F 1200, G11C 2900

Patent

active

061157899

ABSTRACT:
The present invention provides a method and system for providing observability of memory address access for self-timed cache designs. A system according to the present invention for determining which memory location has been accessed in a self-timed cache comprises a content addressable memory; a secondary memory coupled to the content addressable memory, wherein the secondary memory includes at least one memory location which may be selected by the content addressable memory based upon a self-timed cache access. The system further includes a test circuitry coupled to the content addressable memory, wherein the test circuitry stores a pointer which points to a selected memory location in response to the self-timed cache access of the secondary memory.

REFERENCES:
patent: 4392201 (1983-07-01), Brown et al.
patent: 4575792 (1986-03-01), Keeley
patent: 4680760 (1987-07-01), Giles et al.
patent: 4686621 (1987-08-01), Keeley et al.
patent: 4947395 (1990-08-01), Bullinger et al.
patent: 4991081 (1991-02-01), Bosshart
patent: 4996641 (1991-02-01), Talgam et al.
patent: 5031141 (1991-07-01), Guddat et al.
patent: 5165029 (1992-11-01), Sawai et al.
patent: 5195096 (1993-03-01), Moore
patent: 5249281 (1993-09-01), Fuccio et al.
patent: 5289403 (1994-02-01), Yetter
patent: 5325367 (1994-06-01), Dekker et al.
patent: 5394403 (1995-02-01), Klein
patent: 5535164 (1996-07-01), Adams et al.
patent: 5537572 (1996-07-01), Michelsen et al.
patent: 5544342 (1996-08-01), Dean
patent: 5550974 (1996-08-01), Pennington et al.
patent: 5563833 (1996-10-01), Adams et al.
patent: 5572707 (1996-11-01), Rozman et al.
patent: 5614838 (1997-03-01), Jaber et al.
patent: 5651013 (1997-07-01), Iadanza
patent: 5708624 (1998-01-01), Leung
patent: 5793941 (1998-08-01), Pencis et al.
patent: 5802070 (1998-09-01), Adams et al.
patent: 5905680 (1999-05-01), Bosshart
Zhong J. Deng, Nobuyuki Yoshikawa, Stephen R. Whiteley, and Theodore Van Duzer, University of California, IEEE Trans., Data Driven Self-Timed RSFQ Digital Integrated Circuit and System, pp. 3634-3637, Jun. 1997.
E. Brunvand, University of Utah, IEEE Trans., The NSR Processor, pp. 428-435, 1993.

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