Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
1999-01-25
2001-08-14
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
With measuring or testing
37, 37, 36, 36, 36, C702S035000, C702S081000, C702S185000
Reexamination Certificate
active
06274394
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit (IC) testing technology, and more particularly, to a method and system for determining the fail patterns of fabricated wafers in an automated Wafer Acceptance Test (WAT).
2. Description of Related Art
In IC fabrication, there are many factors that affect the acceptance of the fabricated wafers. Therefore, a wafer is typically formed with some testing structures together with the internal circuitry of the wafer for the purpose of performing testing on the internal circuitry of the wafer. As a standard practice, fabricated wafers should undergo the what is known as a Wafer Acceptance Test (WAT) procedure to check whether they are acceptable. However, since each fabrication process produces a very great quantity of wafers, it is not feasible to perform the WAT procedure on all the fabricated wafers. Typically, only a number of randomly selected samples from each lot are tested. A WAT procedure typically includes a number of different test items performed separately on the selected samples, and the results from these test items are then analyzed by statistical methods to cover all the fabricated wafers in the lot.
A wafer is typically formed with a test fixture, called kerf-macro structure, in the kerf between the various dice in the wafer, which can be used to perform various test items on the wafer for the purpose of collecting parametric test data from the wafer. These parametric test data can help determine the health-of-line of the wafer fabrication process to judge whether the fabricated wafers are acceptable or not. These data can also help determine the problems in the fabrication process that cause the rejection so that the problems can be corrected.
The foregoing testing is performed on a randomly selected set of samples from all the fabricated wafers in each lot, and the results are then extended by statistical methods to cover all the fabricated wafers in the lot. However, since the amount of the test data is quite enormous, only a small portion thereof is used by the test engineer group for analysis. By conventional testing methods, since all the test items are analyzed individually rather than collectively from the fail patterns thereof, the results may be inadequate to point out some particular problems in the fabrication process.
As a summary, conventional testing methods have the following drawbacks. First, the test items are analyzed individually rather than collectively, so that the results may be inadequate. Second, it is impossible to perform analysis from the correlation of the test data with the fabrication equipment, fabricated wafers, and lots. Third, the use of the test data for analysis is inadequate.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a method and system for determining the fail patterns of fabricated wafers in an automated WAT procedure, which can analyze the test data in a collective manner from the fail patterns of the fabricated wafers.
It is another objective of the present invention to provide a method and system for determining the fail patterns of fabricated wafers in an automated WAT procedure, which can perform analysis from the correlation of the test data with the fabrication equipment, fabricated wafers, and lots so that the test data can be more fully utilized than in the prior art.
In accordance with the foregoing and other objectives of the present invention, a method and system is provided for determining the fail patterns of fabricated wafers in an automated WAT procedure. First, a WAT procedure having N test items is performed on the selected samples, from which a total of N fail percentages are respectively obtained from the N test items. Next, the N fail percentages are formulated as an N-dimensional test-result vector, in which the (i)th element represents the fail percentage of the (i)th test item, for i=1 to N. Subsequently, an N×N conversion matrix is provided to convert the N-dimensional test-result vector into an N-dimensional fail-pattern vector with fail patterns as basis. In this fail-pattern vector, the (j)th element represents the percentage of the (j)th fail pattern, for j=1 to N.
By the method and system of the invention, the results from the WAT procedure can be extended to all the lots of fabricated wafers. It also allows the test engineer group to have a collective overview on the statistics of the test results and perform analysis from the correlation of the test data with the fabrication equipment, fabricated wafers, and lots so that the test data can be more fully utilized than in the prior art.
REFERENCES:
patent: 5406522 (1995-04-01), Hirano
patent: 5475624 (1995-12-01), West
patent: 5771243 (1998-06-01), Lee et al.
patent: 5963881 (1999-10-01), Kahn et al.
Berry Renee R.
Huang Jiawei
Nelms David
Patents J.C.
ProMOS Technologies Inc.
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