Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2006-11-21
2006-11-21
Tu, Christine T. (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S704000
Reexamination Certificate
active
07139944
ABSTRACT:
A method and system for determining minimum post production test time on an integrated circuit device to achieve optimal reliability of that device utilizing defect counts. The number of defective cells or active elements with defective cells (DEFECTS) on the integrated circuit device are counted and this count serves as a basis for determining the minimum test time. A higher number of DEFECTS results in longer post production testing in order to achieve optimum reliability of the integrated circuit device. The number of DEFECTS can be counted on a device internal to the integrated circuit device and made available to determine the minimum required test time. The number of DEFECTS can also be obtained external to the integrated circuit device by intercepting information routed to another device. Information provided internally and externally can also reveal the physical location of DEFECTS to further refine the minimum required test time.
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Thomas S. Barnett, Adit D. Singh and Victor P. Nelson; “Estimating Burn-In Fall-Out for Redundant Memory”, Department of Electrical and Computer Engineering, Auburn University, Auburn, AL 36849, 8 pages.
Barbour Tange Nan
Barnett Thomas S.
Grady Matthew Sean
Huott William Vincent
Ouellette Michael Richard
Tu Christine T.
Walsh Robert A.
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