Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-09-17
2001-01-23
Lintz, Paul R. (Department: 2768)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06178539
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to determination of critical area and, more particularly, to a method and system for computing critical areas for predicting yield for semiconductor devices.
2. Description of the Related Art
Critical area of a very large scale integration (VLSI) layout is a measure that reflects the sensitivity of the layout to defects occurring during the manufacturing process. Critical area is widely used to predict the yield of a VLSI chip. Yield prediction is essential in today's VLSI manufacturing due to the growing need to control cost. Models for yield estimation are based on the concept of critical area which represents the main computational problem in the analysis of yield loss due to spot defects during fabrication. Spot defects are caused by particles such as dust and other contaminants in materials and equipment and are classified into two types: “extra material” defects causing shorts between different conducting regions and “missing material” defects causing open circuits.
Extra material defects appear most frequently in a typical manufacturing process and are the main reason for yield loss. The yield of a chip, denoted by Y, is computed as
Y
=
∏
i
=
1
m
Y
i
where Yi is the yield associated with the ith step of the manufacturing process. The yield of a single processing step is modeled as
Y
i
=
(
1
+
dA
c
α
)
-
α
where d denotes the average number of defects per unit of area, a the clustering parameter, and A
c
, the critical area.
For a circuit layout C, the critical area is defined as
A
c
=
∫
0
∞
A
(
r
)
D
(
r
)
ⅆ
r
where A(r) denotes the area in which the center of a defect of radius r must fall in order to cause circuit failure and D(r) is the density function of the defect size. The defect density function has been estimated as follows:
D
(
r
)
=
{
cr
q
r
0
q
+
1
,
0
≤
r
≤
r
0
cr
0
p
-
1
r
p
,
r
0
≤
r
≤
∞
(
EQ
.
1
)
where p, q are real numbers (typically p 3, q=1), c=(q+1)(p−1)(q+p), and r
0
is some minimum optically resolvable size.
Existing methods for yield prediction and critical area computation can be classified into the following types:
1. Geometric methods: Compute A(r) for several different values of r independently. Use the results to approximate A
c
. The methods to compute A(r) are usually based on shape-expansion followed by shape-intersection (see e.g., S. Gandemer et al., “Critical Area and critical levels calculation in IC yield modeling”,
IEEE J. of Solid State
Circuits, vol.35, No 2, February 1988, 158-166.) and have a quadratic flavor. For rectilinear layouts there is also a scan-line method which computes critical areas in multiple layers. (see e.g. J. Pineda de Gyvez, C. Di, “IC Defect Sensitivity for Footprint-Type Spot Defects”, IEEE Trans. on Computer-Aided Design, vol. 11, no 5, 638-658, May 1992)
2. Virtual artwork approach: Build a virtual artwork having the same statistical features as the nominal IC layout. The virtual artwork is arranged in a form allowing easy calculation of the critical area as a function of the defect radius (see e.g., W. Maly, “Modeling of lithography related yield losses for CAD of VLSI circuits” IEEE Transactions on Computer-Aided Design, vol. CAD-4, no 3, 166-177, July 1985.). Accuracy is limited by differences in the detail of the nominal and virtual artworks.
3. Monte Carlo approach: Draw a large number of defects with their radii distributed according to D(r), check for each defect if it causes a fault, and divide the number of defects causing faults over the total number of defects. (See e.g., H. Walker and S. W. Director, “VLASIC: A yield simulator for integrated circuits”, IEEE Trans. on Computer-Aided Design, vol. CAD-5, no 4, 541-556, October 1986.)
4. Grid approach: Assume an integer grid over the layout. Compute the critical radius (the radius of the smallest defect causing a fault at this point) for every grid point (see e.g., I. A. Wagner and 1. Koren, “An Interactive VLSI CAD Tool for Yield Estimation”, IEEE Trans. on Semiconductor Manufacturing Vol. 8, No.2, 1995, 130-138). The method works in O(I
1.5
) time, where I is the number of grid points. The accuracy depends on the density of the grid.
The above approaches suffer from accuracy and complexity problems as described. Therefore, a need exists for an improved approach for computing the critical area for shorts in a single layer of a semiconductor device. A further need exists for a low polynomial algorithm for computing critical area for shorts with improved accurately and reduced complexity.
SUMMARY OF THE INVENTION
A method for computing critical area for shorts of a layout, in accordance with the present invention, includes the steps of computing a Voronoi diagram for the layout, computing a second order Voronoi diagram to arrive at a partitioning of the layout into regions, computing critical area within each region and summing the critical areas to arrive at a total critical area for shorts in the layout.
A method for predicting yield based on critical area for shorts of a layout of a circuit, includes the steps of computing a Voronoi diagram for the layout, computing a second order Voronoi diagram to arrive at a partitioning of the layout into regions, computing critical area within each region, summing the critical areas to arrive at a total critical area for short in the layout and predicting a sensitivity to defects of the layout based on the total critical area.
In particularly useful methods, the step of decomposing each region into shapes for calculating the critical areas is preferably included. The step of computing critical area may include the step of computing the critical area according to the following equation:
A
c
=
∫
0
∞
A
(
r
)
D
(
r
)
ⅆ
r
,
where A
c
is the critical area, A(r) is the area of the critical region for defects of radius r and D(r) is a defect density function. The defect density function may include the defect size distribution D(r)=r
0
2
/r
3
where r denotes spot defect radius and r
0
denotes a constant size. The areas for the regions may be classified such that some areas contribute to the critical area and other subtract from the critical area.
The Voronoi diagram and the second order Voronoi diagram preferably include an L
∞
distance metric. The step of computing the Voronoi diagram and the step of computing the second order Voronoi diagram preferably include the step of computing them using a plane sweep or sweep line algorithm. The method may further include the step of computing areas for regions of the layout associated with shapes having edges with a slope of ±1 or horizontal and vertical edges. The method may further include the step of adapting computations of areas for the regions of the layout associated with shapes having edges with any slope. The step of summing the critical areas may include the steps of adding areas that contribute to the total critical areas, subtracting areas that reduce the total critical area and ignoring other areas.
A computer based system for computing critical area for shorts of a layout, includes means for computing a Voronoi diagram for the layout and a second order Voronoi diagram using a sweep line algorithm to arrive at a partitioning of the layout into regions. Also, included are means for computing critical area within each region and means for summing the critical areas to arrive at a total critical area for shorts in the layout.
In alternate embodiments of the system, means for decomposing each region into shapes for calculating the critical areas may be included. The shapes may include at least one of triangles, rectangles and trapezoids. The means for computing critical area may include means for computing the critical area according to the following equation:
A
c
=
∫
0
∞
A
(
r
)
D
(
r
)
ⅆ
r
,
where A
c
is the critical area
Lee Der-Tsai
Papadopoulou Evanthia
F. Chau & Associates,LLP
International Business Machines - Corporation
Lintz Paul R.
Thompson Annette M.
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