Method and system for detecting phase-locked loop (PLL)...

Details Method and system for detecting phase-locked loop (PLL)... Method and system for detecting phase-locked loop (PLL)...

2005-05-17

2005-05-17

Park, Ilwoo (Department: 2182)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Correction for skew, phase, or rate

C713S500000, C714S048000, C714S700000

Reexamination Certificate

active

06895525

ABSTRACT:
An electronic system includes a reference clock that generates a reference clock signal, at least one, phase-locked loop clock generator that synthesizes a derivative clock signal from the reference clock signal, and at least one digital circuit timed by the derivative clock signal. In addition, the electronic system includes a phase-locked loop clock synthesis fault detector having a phase detector and data storage for storing a historical indication of the phase of the derivative clock signal synthesized from the reference clock signal. The phase detector detects a change of phase of the derivative clock signals relative to the historical indication of the phase and, in response to this detection, signals that a clock synthesis fault has occurred.

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patent: 5673004 (1997-09-01), Park
patent: 6177820 (2001-01-01), Nakamura
patent: 6195758 (2001-02-01), Lundh et al.
patent: 0 385 404 (1990-09-01), None

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