Method and system for designing test circuit in a system on...

Details Method and system for designing test circuit in a system on... Method and system for designing test circuit in a system on...

2007-10-03

2010-02-02

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C714S726000, C714S727000, C714S728000, C714S729000

Reexamination Certificate

active

07657854

ABSTRACT:
A method and system for designing a test circuit in a System on Chip (SOC) includes identifying the test design constraints of the test circuit. The SOC is partitioned logically into a first set of logic blocks and a second set of logic blocks. A first set of scan chains is inserted in the first set of logic blocks, and a second set of scan chains is inserted in the second set of logic blocks, based on the test design constraints. Bypass circuits are inserted in the paths of the second set of scan chains, which are capable of bypassing at least one logic block of the second set of logic blocks during testing of the SOC.

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