Electrical computers and digital processing systems: memory – Address formation – Generating a particular pattern/sequence of addresses
Reexamination Certificate
2000-09-13
2004-03-23
Gossage, Glenn (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Generating a particular pattern/sequence of addresses
C711S220000, C365S230060, C365S238500
Reexamination Certificate
active
06711664
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to decoding of addresses and more particularly to method and system for decoding a row address to assert multiple adjacent rows in a memory structure.
BACKGROUND OF THE INVENTION
Superscalar microprocessors may seek to simultaneously execute multiple instructions. Such microprocessors include memory arrays (such as instruction caches) that enable multiple instructions to be simultaneously fetched (i.e. read from the memory array) and fed into an execution unit or pipeline. With such microprocessors, instructions that are to be fetched together may be stored in adjacent rows of the memory array. Thus, the memory array must support the simultaneous reading of the adjacent rows.
Conventional superscalar microprocessors have provided additional ports in the memory arrays to facilitate simultaneous retrieval of adjacent rows. For example, if a microprocessor supports the simultaneous reading of eight instructions from the memory array, the memory array includes eight ports to receive the corresponding row addresses. Unfortunately, the use of such a large number of ports (e.g. eight ports) may waste die area on the microprocessor, as the ports occupy a fairly large amount of space on the microprocessor.
SUMMARY OF THE INVENTION
The present invention addresses the above-described limitation by providing an approach that enables a single row address for a memory structure to be decoded so that multiple rows in the memory structure may be asserted so as to be simultaneously read. This approach decreases the number of ports required for the memory structure. In some cases, only a single port may be required. For example, eight rows of a memory array may be simultaneously read in response to a single row address in an embodiment of the present invention. The present invention may provide decoding logic that automatically causes the rows logically adjacent to an addressed row (i.e., the row identified by the row address) to be asserted in response to a single row address. Hence, each row has a decoder that asserts the row in response to a range of row addresses.
In accordance with one aspect of the present invention, a memory array includes rows of storage cells and a single access port. The memory array also includes decoding logic for asserting a read signal for simultaneously reading a selected one of the rows and a predetermined number of the rows that are adjacent to the selected one of the rows in response to a read request received at the access port. An identifier of the selected row is provided by the read request. This memory array may be found within a microprocessor and separate decoders may be provided for the respective rows.
In accordance with another aspect of the present invention, a row address decoder is provided for decoding a received row address. A selected row is associated with the decoder and is part of a memory array that has rows addressed in sequence. The decoder includes a first component and a second component. The first component asserts the selected row if an integer portion of a result of dividing the selected row address by a number of rows to be simultaneously asserted is equal to an integer portion of a result of dividing the received row address by the number of rows to be simultaneously asserted and if the row address of the selected row follows or is equal to the received row address in the sequence. The second component asserts the selected row if an integer portion of the row address of the selected row divided by the number of rows to be simultaneously asserted exceeds by one an integer portion of the received row address divided by the number of rows to be simultaneously asserted and if the row address of the selected row minus the received row address does not exceed the number of rows to be simultaneously asserted minus one. The components may include logic gates and the like.
In accordance with a further aspect of the present invention, a method of decoding a read address having most significant bits and least significant bits to facilitate simultaneous reading of successive rows in a storage device is practiced. In accordance with this method, the most significant bits of the read address are converted into a fully decoded format to produce a fully decoded vector. The least significant bits of the read address are converted into a priority decoded format to produce a priority decoded vector. For each row in the storage device, logical operations are performed on at least one bit in the fully decoded vector and at least one bit in the priority decoded vector to determine whether to read the row.
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Eisenberg Jason
Gold Spencer M.
Gossage Glenn
Lahive & Cockfield LLP
Sun Microsystems Inc.
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