Method and system for debugging using replicated logic

Details Method and system for debugging using replicated logic Method and system for debugging using replicated logic

2005-06-07

2005-06-07

Thompson, A. M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06904576

ABSTRACT:
A method and apparatus is provided to debug using replicated logic. A text representation of a circuit is compiled to generate a first register transfer level (RTL) netlist. The netlist may be mapped to a target architecture, such as a field programmable gate array (FPGA). The netlist may be used to program an FPGA to create a prototype board for debugging. After debug, a portion of the circuit that a designer would like to analyze is selected. The selected portion of the circuit is replicated. Delay logic is inserted to delay the inputs into the replicated portion of the circuit. The text representation of the circuit is recompiled to generate a second RTL netlist. The second RTL netlist may be mapped to a target architecture, such as a FPGA or application specific integrated circuit (ASIC).

REFERENCES:
patent: 5056094 (1991-10-01), Whetsel
patent: 5452239 (1995-09-01), Dai et al.
patent: 5495487 (1996-02-01), Whetsel, Jr.
patent: 5706473 (1998-01-01), Yu et al.
patent: 6014510 (2000-01-01), Burks et al.
patent: 6269467 (2001-07-01), Chang et al.
patent: 6438735 (2002-08-01), McElvain et al.
patent: 6516449 (2003-02-01), Masud
patent: 6530073 (2003-03-01), Morgan
patent: 6557145 (2003-04-01), Boyle et al.
patent: 6651227 (2003-11-01), Abadir et al.
patent: 6668364 (2003-12-01), McElvain et al.
patent: 6687882 (2004-02-01), McElvain et al.
patent: 2001/0025369 (2001-09-01), Chang et al.
patent: 2002/0138801 (2002-09-01), Wang et al.
patent: 2003/0079195 (2003-04-01), McElvain et al.
I. Neumann et al., Cell Replication and Redundancy Elimination During Placement for Cycle Time Optimization, 1999 IEEE/ACM International Conference on Computer-Aided Design, Nov. 1999, pp. 25-30.
PCT International Search Report for PCT International Appln No. US03/24601, mailed Apr. 16, 2004 (7 pages).

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