Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-12-11
2011-12-06
Patel, Hetul (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S165000, C711SE12009, C707S813000, C707S814000
Reexamination Certificate
active
08074025
ABSTRACT:
A memory manager that compacts a memory heap and reclaims space allocated to dead entities is disclosed. The memory manager may include threads of a first phase, threads of a second phase, and threads of a third phase. The threads of the first phase may assign a target address to each live entity of the memory heap. The thread of the second phase may update references of the memory heap based upon the target address for each live entity. The threads of the third phase may copy each live entity of the memory heap to its target address.
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Li Xiao Feng
Wang Ligang
Intel Corporation
Patel Hetul
Trop Pruner & Hu P.C.
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