Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2007-10-02
2007-10-02
Ho, Hoai V. (Department: 2827)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S205000, C365S236000
Reexamination Certificate
active
11378777
ABSTRACT:
A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row address. A refresh counter in the DRAM generates refresh row addresses that are used to refresh rows of memory cells. The refresh row addresses are compared to the subsets of row addresses that are stored in the register. In the event of a match, the row of memory cells corresponding to the matching subset of bits is refreshed. The number of refreshes occurring each refresh cycle will depend upon the number of bits in the subset that are omitted from the row address. The memory cells that are unable to retain data bits are identified by a modified sense amplifier.
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