Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-01-10
2002-09-24
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06457163
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to electronic design automation (EDA) tools for physical integrated circuit (IC) layouts, more particularly to a method and system for constructing and manipulating the physical IC layout of a multiple-gate semiconductor device.
2. Description of the Related Art
Hierarchical decomposition technology is typically applied by IC layout designers in the construction of IC layouts. The library is the highest level in an IC layout hierarchical organization, and is composed of a cluster of cells. The cell is the second hierarchical level in such an organization, and is composed of several multiple-gate semiconductor devices. The multiple-gate semiconductor device (hereinafter referred to as MG device) is the basic unit of an IC layout, and represents several transistors sharing a common thin-oxide layer. Referring to
FIG. 1
, a two-gate MG device is manufactured using conventional metal oxide semiconductor (MOS) fabrication technology, and is shown to have a thin-oxide layer
10
, and a polysilicon layer
11
that overlaps thin-oxide layer
10
to form gate areas
12
, which serve as MOS transistor channel areas. Metal layer
13
is disposed inside thin-oxide layer
10
but does not overlap with gate areas
12
. Contact layer
14
is enclosed by metal layer
13
and functions as a pin area, which is a point of connection to other metal-connected regions, for the MG device. The geometrical distances among the shapes of the different layers are constrained by design rules of a fabrication technology that are defined in a fabrication technology file. Due to process precision limitations during IC fabrication, the geometrical distances among the shapes of the different layers should exceed the design rule values to increase the IC production yield.
Referring to
FIG. 2
, a polygon-based layout editor is generally used to construct the IC layout of the MG device. After drawing the IC layout, design rule checking (DRC) is performed to validate the IC layout. If a design rule violation is detected, the process reverts to the layout editor for correcting the design rule violation. Because the conventional polygon-based layout editor only provides primitive polygon-drawing commands, it is error-prone, and several iteration steps may have to be performed to correct all design rule violations. The conventional method of constructing the IC layouts of MG devices with the use of the polygon-based layout editor is thus tedious, labor intensive, and time consuming.
SUMMARY OF THE INVENTION
Therefore, the object of the present invention is to provide a method and system for constructing and manipulating a physical IC layout of a multiple-gate semiconductor device, the method and system allowing the simultaneous creation and correction of the IC layout of the multiple-gate semiconductor device to ensure that relevant design rules defined in a fabrication technology file can be fulfilled without the need for a subsequent design rule checking operation, thereby improving the IC layout productivity.
According to one aspect of the present invention, a method for constructing and manipulating a physical integrated circuit layout of a multiple-gate semiconductor device, wherein the layout is comprised of a plurality of gate glue-blocks interconnected by a plurality of active-layer glue-blocks, comprises the machine-executed steps of:
importing user-defined gate glue-block parameters from a user input device;
creating working shapes of the gate glue-blocks according to the user-defined gate glue-block parameters;
creating working shapes of the active-layer glue-blocks in accordance with the working shapes of adjacent ones of the gate glue-blocks, including the machine-executed steps of: extracting relevant design rules of an applied fabrication technology from a fabrication technology file to determine minimum geometrical distances among the working shapes; and creating the working shapes of the active-layer glue-blocks such that the distances among the working shapes exceed the minimum geometrical distances as defined by the relevant design rules; and
showing the layout thus constructed on a computer monitor.
According to another aspect of the present invention, a system for the automated construction and manipulation of a physical integrated circuit layout of a multiple-gate semiconductor device, wherein the layout is comprised of a plurality of gate glue-blocks interconnected by a plurality of active-layer glue-blocks, comprises:
a monitor for showing the layout thereon;
a user input device operable so as to provide user-defined gate glue-block parameters; and
a shape creator connected to the monitor and the user input device and operable so as to create the layout shown on the monitor, the shape creator including: a gate glue-block creator for creating working shapes of the gate glue-blocks according to the user-defined gate glue-block parameters imported from the user input device; and an active-layer glue-block creator, associated operably with the gate glue-block creator, for creating working shapes of the active-layer glue-blocks in accordance with the working shapes of adjacent ones of the gate glue-blocks, wherein the distances among the working shapes exceed minimum geometrical distances as defined by relevant design rules of an applied fabrication technology.
REFERENCES:
patent: 5620916 (1997-04-01), Eden et al.
patent: 5625568 (1997-04-01), Edwards et al.
patent: 5987086 (1999-11-01), Raman et al.
patent: 6194252 (2001-02-01), Yamaguchi
patent: 6209123 (2001-03-01), Maziasz et al.
Saika et al, “A Two-Dimensional Transistor Placement for Cell Synthesis”, IEEE, Jan. 1997, pp. 557-562.
Siek Vuthe
Spring Soft Inc.
Trop Pruner & Hu P.C.
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