Method and system for constructing a hierarchy-driven chip...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000

Reexamination Certificate

active

06898780

ABSTRACT:
A method and system for performing optical proximity correction (OPC) on an integrated circuit (IC) chip design is disclosed. The system and method of the present invention includes exploding calls on an element list to generate an expanded element list, defining a local cover area for each call on the expanded element list, classifying congruent local cover areas into corresponding groups, and performing an OPC procedure for one local cover area in each group By defining the local cover area for each call and grouping congruent local cover areas, only one OPC procedure (e.g., evaluation and correction) needs to be performed per group of congruent local cover areas. The amount of data to be evaluated and the number of corrections performed is greatly reduced because OPC is not performed on repetitive portions of the IC chip design, thereby resulting in significant savings in computing resources and time.

REFERENCES:
patent: 5740068 (1998-04-01), Liebmann et al.
patent: 6350992 (2002-02-01), Manabe et al.
patent: 6416907 (2002-07-01), Winder et al.
patent: 6601231 (2003-07-01), LaCour
patent: 6620561 (2003-09-01), Winder et al.
patent: 20020100005 (2002-07-01), Anderson et al.
patent: 20020155357 (2002-10-01), LaCour
patent: 20020157068 (2002-10-01), LaCour et al.
patent: 20030014731 (2003-01-01), LaCour
patent: 20030145292 (2003-07-01), Stine et al.
patent: 20030208742 (2003-11-01), LaCour
“Optical Proximity Correction Driven Hierarchy” Filed Mar. 14, 2002 U.S Appl. No. 10/097,419 Aleshin et al.

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