Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2001-07-17
2004-05-18
Elmore, Reba I. (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S154000, C711S168000
Reexamination Certificate
active
06738887
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a system and methodology to permit concurrent execution and update of a microcontroller's program memory. More specifically, the present invention provides a system and methodology for permitting a microcontroller to execute code from random access memory (RAM) while simultaneously allowing a microcontroller to update programmable read-only memory (PROM). A particular utility for the present invention is in microcontroller based applications, including general applicability to any process system capable of addressing data in two distinct memory units, for example, RAM and PROM.
2. Background of the Invention
A minimal microcontroller based system typically uses a microcontroller to execute a program which has been loaded into PROM such as flash electrically erasable programmable read-only memory (EEPROM). While simple and economical, a number of complications arise when there is a requirement to concurrently update the program memory while simultaneously executing out of the same memory. One traditional solution is to divide the program memory into “pages” and execute out of one page while updating another page, which works for some types of memory devices but not for others such as a typical flash EEPROM which must first be erased completely before it can be written. Another classical solution, and as shown in the system
100
of
FIG. 1
, is to divide available program space between volatile RAM
14
and PROM
16
in which the system microcontroller
12
copies its program from PROM to RAM from which it executes while updating PROM. However, as is well understood in the art, the amount of data that can be copied from PROM into RAM is limited by the number of address lines
18
(A
0
. . . A
15
) available to the microcontroller for accessing data in both PROM and RAM, since the microcontroller cannot uniquely separate (i.e., uniquely address) PROM from RAM. The system
100
also includes a memory bus
20
to permit read/write access to both PROM and RAM.
While both of the aforementioned techniques are common, both preclude using the complete microcontroller memory space for normal program code and also require complicated programming algorithms. In the first case, pages are wasted, and in the other case a copy of the code in RAM wastes space. For example, in the system and methodology disclosed in
FIG. 1
, if the RAM and PROM were both 64 k memory, only 32 k of program code from PROM could be copied into RAM since only 16 address lines (i.e., 64 k of address space addressed by address lines A
0
-A
15
) can be accessed by the microcontroller. Moreover, PROM cannot be updated while the controller is accessing code from RAM.
Accordingly, there exists a need to provide an economical solution to the aforementioned difficulties of the prior art to permit concurrent read/write operations from RAM while updating the PROM memory, to provide reset control of the microcontroller and to provide enable/disable control over RAM.
SUMMARY OF THE INVENTION
Broadly defined, the present invention provides a system for allocating and controlling memory read/write operations. In exemplary embodiments, the system includes a bridge circuit disposed between a microcontroller and a first memory (e.g., PROM). The bridge circuit and the microcontroller have read/write access to a second memory. The bridge circuit includes memory mapped registers adapted to map predetermined address locations from the second memory to the first memory to provide concurrent read/write access to the second memory and the first memory.
In system embodiments, the present invention also provides microcontroller system, that comprises a microcontroller, a memory bus, a first memory accessed by the microcontroller over the memory bus, a second memory accessed by the microcontroller over the memory bus, and a bridge circuit disposed between the microcontroller and the second memory. The bridge circuit includes memory mapped registers adapted to map predetermined address locations from the first memory to the second memory.
In method form, exemplary embodiments include a method for concurrent access to a microcontroller's memory. The method comprises the steps of defining a plurality of memory mapped registers; and mapping address locations from a first memory to a second memory to permit read or write operations to the second memory based on the address locations.
In still another exemplary method of the present invention, a method for concurrent access to a microcontroller's memory is provided that includes the steps of defining a plurality of memory mapped registers to map address locations from a first memory to a second memory; determining the value of an address location; and mapping read or write operations to the second memory if the address location matches the address location of the memory mapped registers.
It will be appreciated by those skilled in the art that although the following Detailed Description will proceed with reference being made to preferred embodiments and methods of use, the present invention is not intended to be limited to these preferred embodiments and methods of use. Rather, the present invention is intended to be limited only as set forth in the accompanying claims.
Other features and advantages of the present invention will become apparent as the following Detailed Description proceeds, and upon reference to the Drawings, wherein like numerals depict like parts, and wherein:
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Colpo Yolanda
Garcia Enrique
Bates Allen K.
Elmore Reba I.
Hayes, Soloway, Hennessey Grossman & Hage, P.C.
International Business Machines - Corporation
Pfleger Edmund P.
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