Method and system for communication employing dual slew rates

Details Method and system for communication employing dual slew rates Method and system for communication employing dual slew rates

2007-01-22

2010-12-21

Connolly, Mark (Department: 2115)

Electrical computers and digital processing systems: support

Clock control of data processing system, component, or data...

C713S500000, C710S104000, C710S105000

Reexamination Certificate

active

07856571

ABSTRACT:
A bus for implementation with a computer system, as well as a computer processing device capable of interacting with such a bus, and a method of communicating signals over a bus, are disclosed. In at least one embodiment, the bus is a processor bus that includes a first processor bus portion that communicates first signals, and a second processor bus portion that communicates second signals at times determined independently of the first signals. The first and second signals respectively have first and second slew rates, the first and second slew rates being different from one another.

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Intel, System Bus Overview, Intel Itanium 2 Processor Hardware Developer's Manual, p. 3-1, Jul. 2002

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