Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or...
Reexamination Certificate
1999-08-04
2001-11-27
Robertson, David L. (Department: 2187)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
C711S003000, C711S154000
Reexamination Certificate
active
06324617
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention generally relates to address transmission for data access operations in data processing systems and in particular to address transmission for related data access and cast out operations. Still more particularly, the present invention relates to a combined address transmission for related data access and cast out operations to improve address bus bandwidth utilization and cache performance.
2. Description of the Related Art
High performance data processing systems typically include a number of levels of caching between the processor(s) and system memory to improve performance, reducing latency in data access operations. When utilized, multiple cache levels are typically employed in progressively larger sizes with a trade off to progressively longer access latencies. Smaller, faster caches are employed at levels within the storage hierarchy closer to the processor or processors, while larger, slower caches are employed at levels closer to system memory. Smaller amounts of data are maintained in upper cache levels, but may be accessed faster.
Within such systems, when data access operations frequently give rise to a need to make space for the subject data. For example, when retrieving data from lower storage levels such as system memory or lower level caches, a cache may need to overwrite other data already within the cache because no further unused space is available for the retrieved data. A replacement policy—typically a least-recently-used (LRU) replacement policy—is employed to decide which cache location(s) should be utilized to store the new data.
Often the cache location (commonly referred to as a “victim”) to be overwritten contains only data which is invalid or otherwise unusable from the perspective of a memory coherency model being employed, or for which valid copies are concurrently stored in other devices within the system storage hierarchy. In such cases, the new data may be simply written to the cache location without regard to preserving the existing data at that location.
At other times, however, the cache location selected to received the new data contains modified data, or data which is otherwise unique or special within the storage hierarchy. In such instances, the replacement of data within a selected cache location (a process often referred to as “updating” the cache) requires that any modified data associated with the cache location selected by the replacement policy be written back to lower levels of the storage hierarchy for preservation. The process of writing modified data from a victim to system memory or a lower cache level is generally called a cast out or eviction.
When a cache initiates a data access operation—for instance, in response to a cache miss for a READ operation originating with a processor—typically the cache will initiate a data access operation (READ or WRITE) on a bus coupling the cache to lower storage levels. If the replacement policy requires that a modified cache line be over-written, compelling a cast out for coherency purposes, the cache will also initiate the cast out, but on a subsequent bus cycle. The data access operation thus requires multiple operations, and bus cycles, to complete.
It would be desirable, therefore, to reduce the latency associated with data access operations requiring a victim cast out. It would further be advantageous to improve address bus bandwidth utilization for data access operations requiring a cast out.
SUMMARY OF THE INVENTION
It is therefore one object of the present invention to provide improved address transmission for data access operations in data processing systems.
It is another object of the present invention to provide improved address transmission for related data access and cast out operations in data processing systems.
It is yet another object of the present invention to provide a combined address transmission for related data access and cast out operations to improve address bus bandwidth utilization and cache performance.
The foregoing objects are achieved as is now described. A combined address bus transaction contains the address tag for a data access operation target, the address tag for a victim to be replaced, and the address index field identifying the congruence class including both the target and the victim. Directory state information such as coherency state and/or LRU position for the cast out victim may also be appended to the index field and target and victim address tags within the bus operation. Address bus bandwidth utilization is thereby improved, eliminating duplicate transmission of the index field employed by separate data access and cast out operations in accordance with the existing practice. The victim may be prospectively selected concurrently with the determination of whether the target may be found within the storage device forming the combined address, improving overall performance for that device.
The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description.
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Arimilli Ravi Kumar
Dodson John Steven
Guthrie Guy Lynn
Joyner Jody B.
Lewis Jerry Don
Bracewell & Patterson L.L.P.
International Business Machines - Corporation
Robertson David L.
Salys Casimer K.
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