Method and system for combining page buffer list entries to...

Details Method and system for combining page buffer list entries to... Method and system for combining page buffer list entries to...

2006-09-05

2010-11-16

Patel, Hetul (Department: 2186)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S209000, C711S218000, C711S220000

Reexamination Certificate

active

07836274

ABSTRACT:
Certain aspects of a method and system for combining page buffer list entries (PBLEs) to optimize caching of translated addresses are disclosed. Aspects of a method may include encoding at least two page buffer list entries in a remote direct memory access (RDMA) memory map into at least two contiguous memory locations by utilizing a remainder of a physical address corresponding to the two page buffer list entries. The first memory location of the two contiguous memory locations may comprise a base address and a contiguous length of the first page buffer list entry. The second memory location of the two contiguous memory locations may comprise a virtual address and a contiguous length of the second page buffer list entry.

REFERENCES:
patent: 6981120 (2005-12-01), Barrus et al.
patent: 7299266 (2007-11-01), Boyd et al.
patent: 7506084 (2009-03-01), Moerti et al.
patent: 2005/0144422 (2005-06-01), McAlpine et al.
patent: 2006/0236063 (2006-10-01), Hausauer et al.

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