Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Multiple or variable intervals or frequencies
Reexamination Certificate
1999-03-08
2002-01-01
Heckler, Thomas M. (Department: 2182)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Multiple or variable intervals or frequencies
C712S227000
Reexamination Certificate
active
06336191
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to a method and system for data processing and in particular to an improved method and system for clock compensation in a symmetrical multi-processing system. Still more particularly, the present invention relates to a method and system for clock compensation in a symmetrical multi-processing environment when using instruction level tracing tools.
2. Description of the Related Art
Conventionally, detailed code debugging or analysis in a symmetrical multi-processing system or information handling system can be accomplished by using software-tracing tools. These software tracing tools divert the flow of execution from the regular code to their own code to take the trace. Typically, this usually adds many instructions to the regular path of execution and slows it down considerably, depending on the granularity of the trace.
With the machine executing many more instructions than in regular mode, and the hardware, including the clock, going at regular speed, huge distortions in the trace can be observed, essentially because of the clock interrupt handling code. Therefore, clock “compensation” is necessary in software instruction level tracing tools because they divert the flow of execution from the regular code to their own code to take the trace. Prior art solutions to solve this problem have the clock “compensated” or slowed down while the software-tracing tool is active. However, these solutions do not work very effectively in a symmetrical multi-processor SMP environment where there is no mechanism to force the processor clocks to stay in sync. Another weakness of prior art compensation techniques is the lack of machine speed or workload type related adjustment of the compensation amount that is typically a static value.
Consequently, it would be desirable to provide an improved method and system that compensates all the processor clocks in an SMP environment when using software-instruction level tracing. The subject invention herein solves all of these problems in a new and unique manner that has not been part of the art previously.
SUMMARY OF THE INVENTION
It is therefore one object of the present invention to provide an improved method and system for clock compensation during instruction level tracing.
It is another object of the present invention to provide an improved method and system for clock compensation when using instruction level tracing in a symmetrical multi-processing SMP environment.
It is yet another object of the present invention to provide an improved method and system for linking the machine speed and the type of workload to be traced to the clock compensation amount.
The foregoing objects are achieved as is now described. A method and system within a symmetrical multi-processing system or information handling system are disclosed for compensating all the processor clocks when performing instruction level tracing. The method provides a simple and flexible mechanism to slow down the clock proportionally to the density of the trace. According to the present invention, the method determines two parameters; a trigger and a compensation step. The trigger is defined as the number of instructions in the traced code between clock increments and the compensation step is the number of ticks to add to a clock. When the trigger is equal to one, the clock is incremented at each tracing step by an amount equal to the compensation step multiplied by the number of instructions in the current basic block. When the trigger is greater than one, the compensation step is equal to one and the clock is incremented by one every time the number of instructions since the last compensation is bigger than the trigger. The method and system of the present invention links the trigger and compensation step to the processor speed and the workload to trace thereby allowing accurate clock compensation.
The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description.
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Mealey Bruce Gerald
Smolders Luc Rene
Bracewell & Patterson L.L.P.
Emile Volel
Heckler Thomas M.
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