Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-11-21
2006-11-21
Lin, Sun James (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07139997
ABSTRACT:
Disclosed is a method for checking the operation of an IC mask generation algorithm in which at least a first identifier of the mask generation algorithm is associated with at least a first symbol that is not associated with generating a functional IC feature. The first symbol has a predetermined size and a predetermined shape. A predetermined location on a mask is also associated with the first symbol. A mask diagram on the mask is generated at least partially at the first predetermined location. The size and shape of the mask diagram is then compared with at least a portion of the first predetermined size and the first predetermined shape of the first symbol.
REFERENCES:
patent: 4753901 (1988-06-01), Ellsworth et al.
patent: 5446836 (1995-08-01), Lentz et al.
patent: 6800428 (2004-10-01), Okada et al.
Falk Susan
Jensen Bradley
O Hugh Sung-Ki
Rahim Irfan
Selvaraj Priya
Altera Corporation
Lin Sun James
Martine & Penilla & Gencarella LLP
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