Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-04-22
2008-04-22
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C703S014000
Reexamination Certificate
active
07363603
ABSTRACT:
A method for performing verification includes receiving a design and building for the design an intermediate binary decision diagram set containing one or more nodes representing one or more variables. A first case-splitting is performed upon a first fattest variable from among the one or more variables represented by the one or more nodes by setting the first fattest variable to a primary value, and a first cofactoring is performed upon the intermediate binary decision diagram set with respect to the one or more nodes using an inverse of the primary value to generate a first cofactored binary decision diagram set. A second cofactoring is performed upon the intermediate binary decision diagram set with respect to the one or more nodes using the primary value to generate a second cofactored binary decision diagram set, and verification of the design is performed by evaluating a property of the second cofactored binary decision diagram set.
REFERENCES:
patent: 5502661 (1996-03-01), Glunz
patent: 5623418 (1997-04-01), Rostoker et al.
patent: 5910897 (1999-06-01), Dangelo et al.
patent: 5946472 (1999-08-01), Graves et al.
patent: 6052524 (2000-04-01), Pauna
patent: 6088821 (2000-07-01), Moriguchi et al.
patent: 6301687 (2001-10-01), Jain et al.
patent: 6327687 (2001-12-01), Rajski et al.
patent: 6353806 (2002-03-01), Gehlot
patent: 6359345 (2002-03-01), Suzuki
patent: 6539345 (2003-03-01), Jones et al.
patent: 6634012 (2003-10-01), Zhong et al.
patent: 6651096 (2003-11-01), Gai et al.
patent: 6745160 (2004-06-01), Ashar et al.
patent: 6842750 (2005-01-01), Andreev et al.
patent: 2002/0178432 (2002-11-01), Kim et al.
Peranandam, et al., Transactional Level Verification and Coverage Metrics by Means of Symbolic Simulation.
Jacobi Christian
Janssen Geert
Paruthi Viresh
Weber Kai Oliver
Dillon & Yudell LLP
Dinh Paul
International Business Machines - Corporation
Nguyen Nha
Salys Casimer K.
LandOfFree
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