Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-09-13
2003-03-11
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06532575
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to the field of circuit design and more specifically to a method and system for calculating interconnect moments and delay.
BACKGROUND OF THE INVENTION
Accurate calculation of propagation delay due to circuit interconnects is critical to the design of high speed integrated circuits. Signal paths include the interconnects between the gates of an integrated circuit. The resistive, capacitive, and inductive attributes of the interconnects form gate loads that contribute to signal delay. Accurate calculation of interconnect delays, however, is often time-consuming and expensive. Accordingly, calculating interconnect delay has posed a challenge for integrated circuit designers.
SUMMARY OF THE INVENTION
While known approaches have provided improvements over prior approaches, the challenges in the field of circuit design have continued to increase with demands for more and better techniques having greater efficiency. Therefore, a need has arisen for a new method and system for calculating interconnect response and delay.
In accordance with the present invention, a method and system for calculating interconnect response and delay are provided that substantially eliminate or reduce the disadvantages and problems associated with previously developed systems and methods.
According to one embodiment of the present invention, method for calculating interconnect response and delay is disclosed. An interconnect has more than one node. At least one attribute for each node of the interconnect is determined. An admittance of each node is determined from the attributes. A transfer function coefficient for each node is determined by repeatedly calculating a weighted admittance of a current node from the admittance of the node, and calculating a transfer function coefficient of a next node from the weighted admittance. A transfer function of a predetermined order is determined from the transfer function coefficients. An interconnect response is determined from the transfer function. More specifically, an interconnect delay is determined from the transfer function.
According to another embodiment of the present invention, system for calculating interconnect response and delay is disclosed. A parameter module determines at least one attribute for each node of an interconnect. An admittance module determines an admittance of each node from the attributes. A weighted admittance module calculates a weighted admittance of a node from the admittance of the node. A transfer function module calculates a transfer function coefficient for each node from the weighted admittance and determines a transfer function of a predetermined order from the transfer function coefficients. A response module calculates an interconnect response according to the transfer function. More specifically, a delay module calculates an interconnect delay according to the transfer function.
According to another embodiment of the present invention, interconnect response and delay calculation software embodied in a computer-readable medium is disclosed. The software determines at least one attribute for each node of an interconnect, and determines an admittance of each node from the attributes. A transfer function coefficient for each node is determined by repeatedly calculating a weighted admittance of a current node from the admittance of the node, and calculating a transfer function coefficient of a next node from the weighted admittance. A transfer function of a predetermined order is determined from the transfer function coefficients. An interconnect response is determined from the transfer function. More specifically, an interconnect delay is determined from the transfer function.
Embodiments of the invention may provide numerous technical advantages. A technical advantage of one embodiment is that an admittance of each node is recursively calculated from the attributes of an interconnect. Recursive calculation of the admittance may provide faster calculation of interconnect response and delay than calculating the admittance separately for each individual node. Another technical advantage of one embodiment is that transfer function coefficients are determined by repeatedly calculating weighted admittance, and calculating the transfer function coefficients from the weighted admittance. Determining the transfer coefficients in this manner may allow for more efficient computation of a transfer function, which may be used to compute interconnect coefficients and delay. Additionally, the transfer coefficients computed in this manner may efficiently take into account multiple attributes of the interconnects, allowing for faster, more accurate computation of the interconnect coefficients and delay
Other technical advantages are readily apparent to one skilled in the art from the following figures, descriptions, and claims.
REFERENCES:
Lehther et al, “Moment-Based Techniques for RLC Clock Tree Construction”, IEEE, Jan. 1998.
Baker & Botts L.L.P.
Bowers Brandon
Siek Vuthe
Silicon Graphics Inc.
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