Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-07-11
1998-06-02
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711118, 711154, 711124, 711210, G06F 1200
Patent
active
057617210
ABSTRACT:
A method and system for providing cache coherence despite unordered interconnect transport. In a computer system of multiple memory devices or memory units having shared memory and an interconnect characterized by unordered transport, the method comprises sending a request packet over the interconnect from a first memory device to a second memory device requiring that an action be carried out on shared memory held by the second memory device. If the second memory device determines that the shared memory is in a transient state, the second memory device returns the request packet to the first memory device; otherwise, the request is carried out by the second memory device. The first memory device will continue to resend the request packet each time that the request packet is returned.
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"Overlapping Sweep Algorithm For Transmission Group Resequencing In Computer Communications Networks", IBM Technical Disclosure Bulletin, vol. 31, No. 3, Aug. 1998, pp. 358-362.
Baldus Donald Francis
Duffield Nancy Joan
Hoover Russell Dean
Willis John Christopher
Ziegler Frederick Jacob
Dillon Andrew J.
International Business Machines - Corporation
Swann Tod R.
Thai Tuan V.
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