Electrical computers and digital processing systems: support – Digital data processing system initialization or configuration – Loading initialization program
Reexamination Certificate
2000-04-19
2003-06-24
Butler, Dennis M. (Department: 2185)
Electrical computers and digital processing systems: support
Digital data processing system initialization or configuration
Loading initialization program
C713S001000
Reexamination Certificate
active
06584560
ABSTRACT:
TECHNICAL FIELD OF THE DISCLOSURE
The present disclosure relates in general to computer systems having multiple processors and methods of using the same, and, more particularly, to a method and system for booting a multiprocessor computer.
BACKGROUND OF THE DISCLOSURE
Some tasks performed by computer systems can be broken down into components that can be performed simultaneously. A computer system that includes more than one central processing unit or CPU can achieve greater efficiency by assigning each component of such a task to a different processor so that they can be performed in parallel. Such a computer system is often referred to as a multiprocessor computer system. A multiprocessor computer system has the flexibility to employ a single processor when the task can not be efficiently divided and multiple processors when it can.
Multiprocessor computer systems must be developed in accordance with an architecture that addresses the requirements of several simultaneous processors. Elements of single processor computer system architectures such as use of memory and communication with peripheral devices must be modified so that conflicts do not occur between processors. For example, two processors might both attempt to change a value in memory at the same time. From a hardware standpoint, two processors may be undertaking entirely different tasks such that they would not attempt to change the same memory location. Even then both processors might attempt to use the memory bus at the same time to reach two separate memory locations. Multiple processor computer systems must juggle both logical and physical conflicts brought about by parallel execution of tasks.
Both single processor and multiprocessor computer systems include initialization sequences to attain a specified state from a cold or warm boot. For example, a computer that was disconnected from power during a move would experience a cold boot when it was reconnected to electrical power. A warm boot would occur if the same computer was running normally and the user executed a reboot command. A well known reboot command is the use of CTRL-ALT-DEL on computers using the DOS operating system. Computer system designers can utilize different initialization sequences depending upon whether the system has experienced a cold boot or a warm boot.
Computer systems are programmed to undertake initialization sequences for many reasons. Testing the hardware components is conveniently undertaken prior to use of those components. If a hardware component is not responding as it should, a testing routine will be better able to cope and respond than a routine that is not written with the possibility of hardware failure in mind. Initialization also rebuilds data in volatile memory. Many computer systems employ volatile memory for the bulk of their memory requirements. Such memory does not retain data in the absence of power. For example, capacitors may hold charge that indicates a value in memory. A disruption of power causes the charge to be lost and the previously stored value cannot thereafter be determined. Data about hardware configurations and data stored by an operating system to perform such functions as file management and access must be placed in volatile memory. A particular initialization sequence may be designed to address only one of the previous concerns or may address a different concern entirely.
Initialization sequences in multiprocessor computer systems often address hardware testing and configuration of data in volatile memory in a manner similar to single processor systems. Multiprocessor systems, however, often have other additional issues to address. For example, if the initialization sequence has not been divided into components that can be performed by several processors, the system must determine which processor will initialize the computer. That processor is often called the bootstrap processor or BSP. The initialization of a multiprocessor system may also include forming data for handling conflicts between processors for hardware and logical resources. If the processors are not identical, criteria may be used to choose the processor that will run the initialization sequence. Applying the criteria, however, requires the use of a processor. Some conventional systems, therefore, choose a bootstrap processor, apply the criteria, determine that another processor is better, and reassign the bootstrap processor status. The first processor to be designated as bootstrap processor is often determined by wiring. In other words, one of the processor sockets or slots is wired so that the processor that is in that socket or slot begins the initialization sequence.
The redesignation of the bootstrap processor during the initialization sequence can cause problems. Once a computer system has been assembled, the same processors stay in the same sockets. The initialization sequence can be slowed down if the socket wired to contain the bootstrap processor does not contain the best processor as determined by the criteria. In that case, a processor switch must occur every time initialization occurs. Additionally, program routines designed to facilitate the communications of the processors with the peripherals through interrupts are often configured with respect to the current bootstrap processor. A change in bootstrap processor can cause those system management interrupt routines to become stuck in a loop that hangs the system. Reinstallation of the system management interrupt routines may also take significant time.
An additionally disadvantage of the hardwired bootstrap processor is vulnerability to hardware failure. If the processor that is in the hardwired socket fails, the system may be unable to boot even though the other processors are working. Hardware checks that require a particular processor to begin initialization also cannot be performed unless that processor happens to be located in the hardwired socket.
SUMMARY OF THE DISCLOSURE
A method and system for booting a multiprocessor computer are disclosed that provide one or more significant advantages. None of the advantages, by itself, is critical or necessary to the disclosure.
A computer system is provided that can boot a multiprocessor system without reference to a hardwired precedence among the processors. The computer system includes a plurality of computer processors. A memory bus allows the processors to communicate with a main memory. A second bus connects the processors to an interrupt controller. The second bus includes at least bus request lines. An initialization control circuit that can read and assert signals on the bus request lines is provided. The initialization control circuit includes a memory having data identifying one of the processors. In one specific embodiment, the memory is nonvolatile so that it retains data without power. In another embodiment the memory is volatile and is programmed by the chipset prior to selection of the bootstrap processor. The initialization control circuits directs the system to employ the processor identified in the memory as the chief initialization processor.
A more specific computer system is also provided in which each processor includes a local interrupt controller. The local interrupt controllers are connected to the bus request lines.
A method is provided for booting a multiprocessor computer in which power is provided to an initialization control circuit and the processors of a multiprocessor system. A location in the memory of the initialization control circuit is read to identify one of the processors. Values are asserted by the initialization control circuit on one or more bus request lines connected to the processors. The asserted values correspond to the identified processor. A signal is generated and communicated to the processors. In response to the signal the processors sample the bus request lines. The system is then booted under the control of the processor identified in the memory of the initialization control circuit. A further enhancement of the method groups the processors into clusters and specifi
Kroun Jack
Martinez Armando Jaime
Miller Kevin Lee
Baker & Botts L.L.P.
Butler Dennis M.
Chang Eric
Dell USA L.P.
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