Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1998-10-02
2001-06-05
Ray, Gopal C. (Department: 2181)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C713S002000
Reexamination Certificate
active
06243823
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to processing systems and more particularly to deconfiguring memory at the boot-time of the processing system.
BACKGROUND OF THE INVENTION
Processing systems which include memories and processors oftentimes experience failures. Sometimes these failures are so-called hard errors, from which no recovery is possible. Thereafter the device that has caused the hard error is replaced. On the other hand, oftentimes failures are repeatable or so-called soft errors, which occur intermittently and randomly. Oftentimes these soft errors are repeatable and are localized to a particular memory module within the processing system.
However, it is oftentimes difficult to obtain information in existing conventional systems about the memory soft errors. Also, in conventional processing systems, memory modules are typically not deallocated from the system. Clearly, what is needed is a system for determining the cause of a repeatable or soft error and a system and method for deallocating the particular device associated with the soft error. The system must be easy to implement and cost effective, and should be easily implemented in existing systems. The present invention addresses such a need.
SUMMARY OF THE INVENTION
A method and system for deconfiguring memory in a processing system is disclosed. In one aspect, a processing system is disclosed that comprises a central processing unit (CPU), and a memory coupled to the CPU. The first memory includes a memory array and a memory controller for capturing information concerning the status of the memory array. The processing system includes a service processor for gathering and analyzing status information from the memory controller. The processing system also includes a nonvolatile device coupled to the CPU and the service processor. The nonvolatile device includes a deconfiguration area. The deconfiguration area stores information concerning the status of the memory array from the service processor. The deconfiguration area also provides information for deconfiguring at least a portion of the memory array during a boot time of the processing system.
Accordingly, through the present invention, memory defects are detected during normal computer operations by error detection logic. This detection is utilized during any subsequent boot process by service processor and CPU boot firmware to deallocate the defective memory module. This is accomplished through the use of error status and configuration registers within the memory controller chip and through the use of a deconfiguration area in NVRAM, which provides information directly to the CPU boot firmware.
REFERENCES:
patent: 5732281 (1998-03-01), Summers et al.
patent: 5748877 (1998-05-01), Dollahite et al.
patent: 5844910 (1998-12-01), Niijima et al.
Bossen Douglas Craig
Kitamorn Alongkorn
McLaughlin Charles Andrew
International Business Machines - Corporation
Leeuwen Leslie Van
Ray Gopal C.
Sawyer Law Group LLP
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