Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2007-04-25
2011-11-01
Richards, N Drew (Department: 2895)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S051000, C438S107000, C438S110000, C438S118000, C438S455000, C438S459000, C438S460000, C438S464000
Reexamination Certificate
active
08048717
ABSTRACT:
A method and system and for fabricating 3D (three-dimensional) SIC (stacked integrated chip) semiconductor devices. The system includes a vacuum chamber, a vacuum-environment treatment chamber, and a bonding chamber, though in some embodiments the same physical enclosure may serve more than one of these functions. A vacuum-environment treatment source in communication with the vacuum-environment treatment chamber provides a selected one or more of a hydrogen (H2)-based thermal anneal, an H2-based plasma treatment, or an ammonia (NH3)-based plasma treatment. In another embodiment, a method includes placing a semiconductor chip in a vacuum environment, performing a selected vacuum-environment treatment, and bonding the chip to a base wafer. A plurality of chips formed as dice on a semiconductor wafer may, of course, be simultaneously treated and bonded in this way as well, either before or after dicing.
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Liu Chung-Shi
Mii Yuh-Jier
Sun Yuan-Chen
Yu Chen-Hua
Garcia Joannie A
Richards N Drew
Slater & Matsil L.L.P.
Taiwan Semiconductor Manufacturing Company , Ltd.
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