Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-04-14
1999-04-13
Ellis, Richard L.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711154, G06F 700
Patent
active
058945695
ABSTRACT:
A method and system for back-end gathering of store instructions within a processor is disclosed. In accordance with the method and system of the present invention, a store queue within a data-processing system includes a front-end queue and a back-end queue. A multiple of entries is provided in the back-end queue, and each entry includes an address field, a byte-count field, and a data field. A determination is first made as to whether or not a data field of a last entry of the back-end queue is completely filled. In response to a determination that the data field of the last entry of the back-end queue is not completely filled, another determination is made as to whether or not an address for a store instruction in a subsequent entry is equal to an address for a store instruction in the last entry plus a byte count in the last entry. In response to a determination that the address for a store instruction in a subsequent entry is equal to the address for a store instruction in the last entry plus the byte count in the last entry, the two store instructions are combined into one bus transfer.
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Arimilli Ravi Kumar
Dodson John Steven
Lewis Jerry Don
Dillon Andrew J.
Ellis Richard L.
Henkler Richard A.
International Business Machines - Corporation
Ng Antony P.
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