Method and system for avoiding live lock conditions on a compute

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation

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Details

710108, 710110, 710116, 710120, 710244, 710126, 710129, 710856, 711150, 711151, 711146, 711167, G06F 1336

Patent

active

061417157

ABSTRACT:
A computer system avoids livelock conditions on a computer bus coupled to plural bus masters. In response to receiving a transaction request from a first bus master across the computer bus, a bus controller transmits a retry command to the first bus master if the bus controller is unable to execute the transaction request. A livelock condition is avoided by preventing transaction requests from any of the bus masters, other than the first bus master, from being processed until after the first bus master re-submits the transaction request. The bus controller may prevent execution of the transaction request from the other bus masters by transmitting retry commands to all bus masters that submit transaction requests after the transaction request from the first bus master is received and before the first bus master re-submits the transaction request. Alternatively, the bus controller may prevent the other bus masters from successfully arbitrating access to the computer bus until after the first bus master uses the computer bus to re-submit its transaction request.

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