Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1997-07-16
2001-01-30
Moise, Emmanuel L. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S201000, C365S233100
Reexamination Certificate
active
06182253
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to memory test systems, and more particularly to an automated method and system for identifying SDRAM and SGRAM memories.
BACKGROUND OF THE INVENTION
A substantial industry has evolved for the packaging of integrated circuit (IC) memory devices into subassemblies commonly referred to as memory modules. The memory module is a more practical increment of memory than a single IC, and has enjoyed some industry standardization with regard to means of connection, operating voltages, definition of connector pins, and operation of signals. A representative standards organization is the Joint Electron Device Engineering Council (JEDEC). However, beyond that which has been standardized by industry, there are many attributes of a memory module which cannot be recognized readily by the reading of the part number, or by examination of the ICs on the module. This is a result of the wide variety of end user requirements which are placed upon the manufacture of modules.
For a memory module to be tested correctly, test parameters must be precisely identified. When module testing occurs outside of an automated environment, manual entry of test parameters becomes tedious and prone to human error. In an automated environment, the incorporation of a small non-volatile memory device known as “serial presence detect bits” into a memory module for the storage of memory parameters has not solved the test parameter identification problem. The contents of these non-volatile memories themselves are generally incomplete, not standardized, and not initialized and tested at the point of manufacture.
A synchronous memory test system has been developed which provides for the automatic identification (ID) of synchronous memory modules, and for the purpose of reporting to the operator of the test system the type, configuration, size, and other characteristics of the memory module, and the establishment of all operating parameters necessary for correct testing of the module.
The memory module identification process itself is carried out in a hardware/software state machine which includes a multilayered, nested loop architecture which allows the efficient identification of all necessary memory module attributes.
Anticipating that larger and more diverse synchronous memory modules will be developed in the future, patterns representing possible control line connections are stored in tables. Table storage permits simple updating of the memory module test system without altering the operation or accuracy of the identification process.
U.S. Pat. No. 5,561,636 discloses a RAM memory which has been adapted to include a self-test feature and a plurality of memory cells arranged in rows and columns, means for selecting rows and columns, and means for simultaneously testing a plurality of cells in a plurality of rows to replace non-functioning memory cells with functioning memory cells held in reserve. The memory cells are arranged in segments with sense amplifiers coupled to each column and a second group of sense amplifiers connected to the segment to bring the test feature into effect. The present invention, by way of contrast, identifies any one of a plurality of different synchronous memories rather than a specific pre-defined memory.
U.S. Pat. No. 5,487,042 discloses a DRAM which has been modified to include circuitry that will communicate the characteristics of the DRAM including test patterns to a memory tester to accommodate a highly customized testing for the particular DRAM. By way of contrast, the present invention is not SDRAM or vendor specific, and does not depend upon the SDRAM under test to supply test patterns for use by the memory test system.
U.S. Pat. No. 5,533,194 discloses an SDRAM tester which requires hardware test circuitry to be added to the memory array “board” or memory module to control the testing of the memory array, and uses two different addressing protocols at two different rates to test all memory blocks. By contrast, the present invention uses a single addressing protocol at a single rate, and tests only a representative block in a memory array board.
U.S. Pat. No. 5,301,156 discloses a RAM which has been adapted to include a self-test circuit. The test circuit uses a signature generator to form a test signature from the RAM responses to test patterns, and a scan path to serially shift data into and out of the test circuit. The disclosed apparatus and method must be configured to operate on only a single, specific, pre-defined memory device. By way of contrast, the present invention has the capability to identify a wide variety of synchronous memories, and determines all parameters necessary to test any one of the synchronous memories being identified.
U.S. Pat. No. 5,450,364 discloses a self-refresh system which includes an oscillator coupled to a self-refresh counter, and which generates a signal to indicate that a self-refresh cycle has been completed. U.S. Pat. No. 4,451,903 discloses a method of modifying a RAM, EEPROM or EPROM to include ROM cells which are written with chip parameters including supply voltages, operating currents, programming voltages, and programming pulse-widths, as well as manufacturer's identification and mask sets. No testing occurs. By way of contrast, the present invention does not require or use identification codes stored in or with a memory unit being identified or under test in order to determine the necessary test parameters for the memory unit.
The present invention is further distinguished from U.S. Pat. Nos. 5,561,636; 5,487,042; 5,533,194; 5,301,156; 5,450,364; and 4,451,903 in that the present invention does not require hardware modifications or additions to the memory unit, memory board, or module being identified or tested.
U.S. Pat. No. 5,577,236 discloses a memory controller which is adaptive to read data from synchronous RAM modules in which the memory cells in use may vary without compromising the memory bandwidth. The memory controller has an open loop clock system which includes a system clock, and a sampling clock which provides an assortment of phase-shifted clock signals based upon the system clock. In response to a memory loading, one of the phase-shifted clock signals is selected and thereafter delayed to trigger data latches to accept data read from a memory bank after an appropriate access time. The disclosed method and apparatus requires that memory modules be precharacterized or identified and enumerated, and based upon such information, a phase-shifted sampling clock is preselected. By contrast, the present invention adapts to the memory module access time by adjusting the timing of a data sampling strobe in small increments, until during a test phase the data patterns read are identical to the data patterns written, thereby adapting to any synchronous memory access time without need for any preselections.
U.S. Pat. No. 5,570,381 discloses a method of testing SDRAM memory banks, in which data is written into a first bank at a slow tester speed, transferred between banks at a high full page burst speed, and read by the tester from the second bank at the slower tester speed. The present invention accomplishes the same result by using only the slower tester speed, and a variable word burst transfer. Further, a lower cost synchronous memory tester is made possible by employing a state machine based memory controller that obviates the need for any high-speed clock by controlling the clock enable (CKE) control line to the memory unit being identified.
U.S. Pat. No. 4,606,025 discloses a memory array test system which attempts to match the test requirements of memory arrays of different manufacturers with an array of memory testers from different manufacturers, by providing a universal tester independent language for manually entering parameter tests in accordance with designer specifications, and then using translators to make the test sequence compatible with a particular memory tester. The present invention obviates the need for processing parameters external to the memory
Lawrence Archer R.
Little Jack C.
Baker & Botts L.L.P.
Moise Emmanuel L.
Tanisys Technology, Inc.
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