Method and system for arbitrating between bus masters having div

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation

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Details

710110, 710111, G06F 1336

Patent

active

060887508

ABSTRACT:
A data processing system is disclosed which includes a first processor having an m-byte data width, an n-byte data bus, where n is less than m, and a second processor electrically coupled to the bus which performs bus transactions utilizing n-byte packets of data. An adaptor is electrically coupled between the first processor and the bus which converts n-byte packets of data input from the bus to m-byte packets of data, and converts m-byte packets of data input from the first processor to n-byte packets of data, thereby enabling the first processor to transmit data to and receive data from the bus utilizing m-byte packets of data. In a second aspect of the present invention, a method and system are provided for arbitrating between two bus masters having disparate bus acquisition protocols. In response to a second bus master asserting a bus request when a first bus master controls the bus, control of the bus is removed from the first bus master. Thereafter, in response to a signal transmitted from an arbitration control unit to the first bus master instructing the first bus master to terminate its bus transactions, control of the bus is granted to the second bus master. In response to the second bus master terminating its bus request, control of the bus is granted to the first bus master and a signal is transmitted from the arbitration control unit to the first bus master acknowledging the grant of control.

REFERENCES:
patent: 4987529 (1991-01-01), Craft et al.
patent: 5369748 (1994-11-01), McFarland et al.
patent: 5528767 (1996-06-01), Chen
patent: 5572686 (1996-11-01), Nunziata et al.
patent: 5799160 (1998-08-01), Woodbridge et al.

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