Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-09-30
2008-03-04
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07340706
ABSTRACT:
The present invention provides a method and system for analyzing the quality of an OPC mask. The method includes receiving a target layer from a target design, receiving an OPC mask layer from the OPC mask. The method also includes classifying each cell of at least one of the target layer and the OPC mask layer as either repeating or non-repeating, and for each repeating cell, recognizing geometric points in the target layer to determine quality measuring groups. The method also includes simulating the OPC mask layer based on the quality measuring groups, measuring edge placement errors (EPEs) based on at least one of the geometric points, and providing an EPE layer representing EPEs greater than an EPE threshold.
REFERENCES:
patent: 6704921 (2004-03-01), Liu
patent: 6928634 (2005-08-01), Granik et al.
patent: 6978438 (2005-12-01), Capodieci
patent: 7155698 (2006-12-01), Gennari
patent: 7237221 (2007-06-01), Granik et al.
Aleshin Stanislav V.
Egorov Evgueny E.
Golubtsov Ilya
Medvedeva Marina
Rodin Sergei
Chiang Jack
LSI Logic Corporation
Strategic Patent Group P.C.
Tat Binh
LandOfFree
Method and system for analyzing the quality of an OPC mask does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for analyzing the quality of an OPC mask, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for analyzing the quality of an OPC mask will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3971821